US4042726A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selective oxidation method
Assignee: Hitachi Ltd
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Filing: 1975-09-08
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Granted: 1977-08-16
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Expires: 1995-09-08
Abstract
Abstract A method for manufacturing a semiconductor device wherein semiconductor material is selectively removed from a principal surface of a semiconductor substrate having at least one semiconductor layer formed thereon to provide a groove that extends through said layer and into the substrate and wherein the semiconductor material of the substrate is selectively oxidized to form an oxide insulator layer within the groove. The groove has a width which is smaller than the thickness of the semiconductor layer and the oxide insulator layer serves to isolate a portion of the semiconductor layer from adjacent portions of the substrate.
Inventors
- 👤 Tadao Kaji
- 👤 Tsuneaki Kamei
- 👤 Keiji Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:52
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/69; H10P50/691; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/945; Y10S438/947
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
33 words
A method of manufacturing a semiconductor device which comprises the steps of: 1. forming an insulating film on the principal surface of a semiconductor substrate having at least one semiconductor layer thereon, 2.
Claim 2
Independent Claim
33 words
A method of manufacturing a semiconductor device which comprises the steps of: 1. forming an insulating film on the principal surface of a semiconductor substrate having at least one semiconductor layer thereon, 2.
Claim 3
Dependent Claim
158 words
forming a metallic layer on said insulating film, 3. selectively forming a mask on said metallic layer, 4. applying an etchant to the selectively formed mask and metallic layer to etch said metallic layer beneath an edge of said mask, 5. forming further metallic layer on part of the exposed insulating film so as to leave a gap between areas of metallic material on said insulating film beneath said mask, 6. removing said mask to expose said gap, 7. selectively etching said insulating film and said substrate by way of the gap in the metallic material in the surface of said insulating film to form a groove in said insulating film and said substrate which extends through said layer into said substrate and which has a width smaller than the thickness of said layer, and 8. selectively oxidizing the semiconductor material of said substrate to form an oxide insulator layer in said groove that isolates a portion of
Claim 4
Dependent Claim
158 words
forming a metallic layer on said insulating film, 3. selectively forming a mask on said metallic layer, 4. applying an etchant to the selectively formed mask and metallic layer to etch said metallic layer beneath an edge of said mask, 5. forming further metallic layer on part of the exposed insulating film so as to leave a gap between areas of metallic material on said insulating film beneath said mask, 6. removing said mask to expose said gap, 7. selectively etching said insulating film and said substrate by way of the gap in the metallic material in the surface of said insulating film to form a groove in said insulating film and said substrate which extends through said layer into said substrate and which has a width smaller than the thickness of said layer, and 8. selectively oxidizing the semiconductor material of said substrate to form an oxide insulator layer in said groove that isolates a portion of
Claim 5
Dependent Claim
32 words
the semiconductor layer from adjacent portions of the substrate. 2. A method of manufacturing a semiconductor device according to claim 1, wherein each of said metallic layers is a layer of chromium.
Claim 6
Dependent Claim
19 words
A method of manufacturing a semiconductor device according to claim 2, wherein said mask is made of polyimide resin.
Claim 7
Dependent Claim
46 words
A method of manufacturing a semiconductor device according to claim 1, wherein said groove has a width of from 0.1-2μm and a depth sufficient to provide adequate withstand voltage to the oxide insulator layer formed in the groove to isolate semiconductor elements formed on said substrate.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-15 | 1981-02-14 | 1981-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-15 | 1985-02-14 | 1985-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-15 | 1989-02-14 | 1989-08-16 | $7700.00 | Window Closed / Lapsed |