Analog-to-digital converter using common circuitry for sample-and-hold and integrating functions

Claim 1

A circuit arrangement for converting a time-varying or d-c signal into a digital representation which comprises: timing means; logic means; first switching means; reference voltage means comprising: a full-wave rectifier connected to receive the analog signal; and a low pass filter connected to the output of the full-wave rectifier to reduce the ripple and harmonic voltages generated during rectification; and means for connecting the reference voltage output from said filter means to said first switching means; means for generating a ramp signal comprising: combined sampling, holding and integrating means for timed selection of samples of said signal at intervals set by said timing means, said logic means controlling the connection of said reference voltage via said first switching means to said combined sampling, holding and integrating means; said generating means further comprising: a first operational amplifier having an inverting input connected to receive the signal, a non-inverting input, and an output; second switching means having one end connected to the output of said first operational amplifier; and a second operational amplifier having an inverting input connected to the other end of said first and second switching means; having a non-inverting input connected to ground, and having a capacitor connected between the inverting input and the output; and a feedback means connected between the output of said operational amplifier and the non-inverting input of said first operational amplifier; means for comparing said ramp signal to ground; and means for counting the time duration of the ramp signal for durations less than a predetermined period.