US4041406A
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Method and apparatus for the determination of the transition of digital data signals modulated with two different signal frequencies
Assignee: Wincor Nixdorf International GmbH
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Filing: 1976-07-01
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Granted: 1977-08-09
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Expires: 1996-07-01
Abstract
Abstract A method and apparatus are provided for detecting the transition of digital data signals the two states of which are modulated with two different signal frequencies from one signal frequency to the other signal frequency. Timing elements generate comparison pulses having a first and second duration at each pulse front of the modulated data signal during a second and first signal frequency respectively. The comparison pulses in turn are used to generate control pulses so that the leading edge of the control pulse coincides with the leading edge of the comparison pulse, and likewise, the trailing edge of the control pulse coincides with the trailing edge of the comparison pulse. The control pulses are fed to the up/down counting direction control input of a reversible counter having a clock signal connected to its input. A pair of comparators compare the contents of the reversible counter with a pair of preset separate threshold levels. The comparators generate an output signal upon the attainment of a threshold level in the reversible counter which attainment is interpreted as a transition from one signal frequency to the other signal frequency. The determination of a transition from one signal frequency to the other signal frequency is also utilized to change the duration of the comparison pulse to the duration of the other comparison pulse.
Inventors
- 👤 Lorenz Hanewinkel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:04
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1563
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
175 words
A method for determining the transition between a first and second signal frequency of a data signal wherein the data signal is modulated with different signal frequencies, comprising the steps of: generating a comparison pulse of a first or second duration at each pulse front of said data signal during said second or first signal frequency, respectively, generating a control pulse at the leading edge of each comparison pulse, terminating the control pulse at the trailing edge of each comparison pulse, changing the contents of a storage means in a first direction during said control pulses, changing the contents of said storage means in a direction opposite from said first direction during the intervals between said control pulses, and establishing a pair of separated threshold values whereby the attainment of one of said threshold values by said contents of storage means is interpreted as a transition of the data signal from one signal frequency to the other signal frequency, which transition is also used for the change over of the duration of the comparison pulses.
Claim 2
Independent Claim
175 words
A method for determining the transition between a first and second signal frequency of a data signal wherein the data signal is modulated with different signal frequencies, comprising the steps of: generating a comparison pulse of a first or second duration at each pulse front of said data signal during said second or first signal frequency, respectively, generating a control pulse at the leading edge of each comparison pulse, terminating the control pulse at the trailing edge of each comparison pulse, changing the contents of a storage means in a first direction during said control pulses, changing the contents of said storage means in a direction opposite from said first direction during the intervals between said control pulses, and establishing a pair of separated threshold values whereby the attainment of one of said threshold values by said contents of storage means is interpreted as a transition of the data signal from one signal frequency to the other signal frequency, which transition is also used for the change over of the duration of the comparison pulses.
Claim 3
Dependent Claim
26 words
Method according to claim 1, characterized in that the change of the contents of the storage means in opposite directions is brought about at different speeds.
Claim 4
Dependent Claim
38 words
Method according to claim 2, characterized in that the change of the contents of the storage means is brought about by speeds which at constant signal frequency, result in about the same extreme values of the storage contents.
Claim 5
Dependent Claim
41 words
Method according to claim 1, characterized in that the change-over of the duration of the comparison pulses is brought about by a comparison of the contents of the storage means with said separated threshold values, which comparison is carried out continuously.
Claim 6
Dependent Claim
26 words
The method according to claim 1, and characterized in that during the higher frequency data signal, the control pulses are generated only during overlapping comparison pulses.
Claim 7
Dependent Claim
119 words
A circuit arrangement for generating said control pulses according to claim 1 comprising at least two pulse-front controlled time elements having their inputs operatively coupled to the data signal, wherein said time elements generate the comparison pulses of different duration which are fed into the first inputs of two first AND gates, that the second inputs of said AND gates are connected with a circuit means which generate signals representative of the existence of either the first or the second data signal frequency and that the outputs of the two AND gates are fed via an OR gate into the control input of a reversible counter wherein said control pulses are generated at the output of said OR gate.
Claim 8
Dependent Claim
83 words
A circuit arrangement according to claim 6, wherein for the generation of one of said comparison pulses, one of said time elements comprises two second time elements, one of which is triggered only by the leading edge of said data signal and the other of which is triggered only by the trailing edge of the data signal wherein the outputs of the second time elements are connected with the first input of one of the first AND gates via a second AND gate.
Claim 9
Dependent Claim
58 words
A circuit arrangement according to claim 6, wherein the output of the reversible counter is connected to the first comparison input of two comparators and including means for feeding one of said threshold values into the second comparison input of one of said comparators and the other threshold value into the second comparison input of the other comparator.
Claim 10
Dependent Claim
43 words
A circuit arrangement according to claim 8, wherein the outputs of the two comparators are connected to opposite inputs of a flip-flop wherein the outputs of the flip-flop signalize the existence of the first or the second signal frequency of said data signal.
Claim 11
Dependent Claim
42 words
A circuit arrangement according to claim 6, wherein the control input of the reversible counter is connected with its counter input via an AND gate wherein the second input of said last mentioned AND gate is coupled to an operational clock cycle.
Claim 12
Dependent Claim
83 words
A circuit arrangement according to claim 10, wherein the last mentioned AND gate is connected with the counter input via an OR gate having its second input coupled to the output signal of an AND gate which is enabled by an inverted version of the signal at the control input of the reversible counter, the second input of the last mentioned AND gate being coupled to the output of a frequency division means which divides the operational clock cycle by a predetermined ratio.
Claim 13
Dependent Claim
44 words
A circuit arrangement according to claim 11, wherein said frequency division means further comprises a binary counter, the outputs of which are connected with a decoder adapted to generate a predetermined number of output pulses in response to a predetermined number of input pulses.
Claim 14
Dependent Claim
14 words
A circuit arrangement according to claim 6, wherein said time elements are binary counters.
Claim 15
Dependent Claim
29 words
A circuit arrangement according to claim 6, and including an interlock circuit coupled to the reversible counter and adapted to limit the upper and lower count in said counter.
Claim 16
Dependent Claim
21 words
A circuit arrangement according to claim 14, wherein the interlock circuit is controlled by the output signals generated by the comparators.
Claim 17
Independent Claim
198 words
An apparatus for determining the transition between a first and second signal frequency of a data signal wherein the data signal is modulated with different signal frequencies, comprising: means for generating a comparison pulse of a first or second duration at each pulse front of said data signal during said second or first signal frequency, respectively, means for generating a control pulse at the leading edge of each comparison pulse and for terminating the control pulse at the trailing edge of each comparison pulse, means for changing the contents of a storage means in a first direction during said control pulses and for changing the contents of said storage means in a direction opposite from said first direction during the intervals between said control pulses, and means for establishing a pair of separated threshold values, and means for comparing the contents of said storage means with said threshold values whereby the attainment of one of said threshold values by contents of said storage means is interpreted as a transition of the data signal from one signal frequency to the other signal frequency, which transition is also used for the change over of the duration of the comparison pulses.
Claim 18
Independent Claim
198 words
An apparatus for determining the transition between a first and second signal frequency of a data signal wherein the data signal is modulated with different signal frequencies, comprising: means for generating a comparison pulse of a first or second duration at each pulse front of said data signal during said second or first signal frequency, respectively, means for generating a control pulse at the leading edge of each comparison pulse and for terminating the control pulse at the trailing edge of each comparison pulse, means for changing the contents of a storage means in a first direction during said control pulses and for changing the contents of said storage means in a direction opposite from said first direction during the intervals between said control pulses, and means for establishing a pair of separated threshold values, and means for comparing the contents of said storage means with said threshold values whereby the attainment of one of said threshold values by contents of said storage means is interpreted as a transition of the data signal from one signal frequency to the other signal frequency, which transition is also used for the change over of the duration of the comparison pulses.
Claim 19
Dependent Claim
23 words
The apparatus as defined in claim 16, and including means for limiting the contents of said storage means between the separated threshold values.
Claim 20
Dependent Claim
31 words
The apparatus as defined in claim 16, wherein said storage means comprises a reversible counter and wherein said control pulses are coupled to the direction control input of said reversible counter.
Claim 21
Dependent Claim
55 words
The apparatus as defined in claim 18, and including frequency division means coupled to the counting input of said reversible counter and adapted to provide a first predetermined counting frequency to said reversible counter during said control pulses and a second predetermined counting frequency to said reversible counter during the interval between said control pulses.
Claim 22
Dependent Claim
37 words
The apparatus as defined in claim 16, wherein said means for generating comparison pulses comprises at least two timing elements adapted to generate output pulses of a predetermined duration at each pulse front of said data signal.
Claim 23
Dependent Claim
67 words
The invention as defined in claim 16, and further comprising a first comparator for comparing the contents of said storage means with one threshold value and a second comparator for comparing the contents of said storage means with the other threshold value, wherein each comparator generates an output signal upon the attainment of its respective threshold value in said storage means representative of the threshold value attained.
Claim 24
Dependent Claim
33 words
The invention as defined in claim 21, wherein the outputs of the comparators are coupled to opposite inputs of a flip-flop circuit the output of which is indicative of the data signal frequency.
Claim 25
Dependent Claim
32 words
The invention as defined in claim 16, wherein the means for generating a control pulse at the higher signal frequency further comprises means for generating said control pulse during overlapping comparison pulses.
References Cited (Backward Citations)
US3908169A
Cited
US3979685A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-08 | 1981-02-07 | 1981-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-08 | 1985-02-07 | 1985-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-08 | 1989-02-07 | 1989-08-09 | $7700.00 | Window Closed / Lapsed |