Signal processing devices using residue class arithmetic

Claim 2

Apparatus for performing arithmetical calculations on a plurality, N, of digital input signals, utilizing residue class arithmetic, comprising: a plurality N of means for coding the N input digital signals into digital modulo m i integers, K≦i≧1; a plurality N of means, each means having an input connected to each coding means, for converting the digital modulo m i integers into corresponding analog modulo m i signals; a plurality N of means for performing a mathematical operation on analog modulo m i integers, each means having an input connected to a D/A converting means; a plurality N of means, connected to the N operation means, for converting the analog modulo m i integers from the operation means into digital modulo m i integers; and means, connected to the N A/D converting means, for decoding the digital modulo m i numbers into digital outputs.

Claim 3

The apparatus according to claim 1, wherein: the means for performing the mathematical operation comprises a multiplier.

Claim 4

The apparatus according to claim 1, wherein: the means for performing the mathematical operation comprises a correlator.

Claim 5

Apparatus for performing arithmetical calculations on a plurality, N, of digital input signals, utilizing residue class arithmetic, comprising: a plurality N of means for coding the N input digital signals into digital modulo m i integers, K≦i≧1; a plurality N of sets of means, one set connected to each coding means, K means per set, for converting the digital modulo m i integers into corresponding analog modulo m i signals; a plurality K of means for performing a mathematical operation on analog modulo m integers, each means having N inputs, one from, and connected to, each of the sets of the D/A converting means; a plurality K of means, connected to the K operation means, for converting the analog modulo m i integers from the operation means into digital modulo m i integers; and means, connected to the K A/D converting means, for obtaining the resultant, a*b* . . . *n modulo m i , of the mathematical operations on the N digital inputs.

Claim 6

Apparatus for performing arithmetical calculations on a plurality, N, of digital input signals, utilizing residue class arithmetic, comprising: a plurality N of means for coding the N input digital signals into digital modulo m i integers, K≦i≧1; a plurality N of sets of means, one set connected to each coding means, K means per set, for converting the digital modulo m i integers into corresponding analog modulo m i signals; a plurality K of means for performing a mathematical operation on analog modulo m integers, each means having N inputs, one from, and connected to, each of the sets of the D/A converting means; a plurality K of means, connected to the K operation means, for converting the analog modulo m i integers from the operation means into digital modulo m i integers; and means, connected to the K A/D converting means, for obtaining the resultant, a*b* . . . *n modulo m i , of the mathematical operations on the N digital inputs.

Claim 7

The apparatus according to claim 4, wherein: the means for performing the mathematical operation comprises a multiplier.

Claim 8

The apparatus according to claim 4, wherein: the means for performing the mathematical operation comprises a correlator.

Claim 9

The apparatus according to claim 4, wherein N is equal to two and the correlator is a cross correlator comprising: a pair of delay lines each having an even number 2 P of taps and outputs, one end of one delay line being connected to a first D/A converting means, which processes a first digital input signal, a modulo m, the opposite end of the other delay line being connected to a second D/A converting means, which processes the second digital input signal, b modulo m; a plurality 2 P of means for multiplying, whose two inputs comprise corresponding outputs of the delay lines, for multiplying its two input signals; a set of pairs of analog-to-digital converting means, each means connected to the output of a multiplier, for converting an analog modulo-m input number into a digital modulo-m output number; a first set of 1/2 2 P , P=1, 2, 3, . . . , means connected to the outputs of the converting means, for summing the digital modulo m input signals; a second set of 1/4(2 P ) means, each means having its two inputs connected to two of the first set of summing means, for summing its digital input signals; a third, fourth, . . . , set of 1/8 (2 P ), 1/16(2 P ), . . . , means, each means having its two inputs connected to one of the preceding pairs of summing means, until there remains one summing means, at the output of which appears a*b modulo m.

Claim 10

Apparatus for performing arithmetical calculations on a plurality of digital input signal a i , i=0, 1, 2, . . . , N-1, utilizing residue class arithmetic, comprising: a means for coding the input digital signal into digital a i modulo m k integers, k = 1, 2, . . . , t;

Claim 11

Apparatus for performing arithmetical calculations on a plurality of digital input signal a i , i=0, 1, 2, . . . , N-1, utilizing residue class arithmetic, comprising: a means for coding the input digital signal into digital a i modulo m k integers, k = 1, 2, . . . , t;

Claim 12

a plurality N of means, each means having an input connected to the coding means, for converting the digital a i modulo m k integers into corresponding analog a l modulo m k signals; a plurality t of means for delaying the analog a i modulo m k integers, each means having an input connected to a D/A converting means, each delaying means having N outputs, h i mod m k ; a plurality t of means, connected to the delaying means, for summing the outputs of the delaying means; a plurality t of means, connected to the t summing means, for converting the analog a i modulo m k integers from the summing means into digital a i modulo m k integers; and means, connected to the t A/D converting means, for decoding the digital a i modulo m k numbers into a digital output, ##EQU6##

Claim 13

a plurality N of means, each means having an input connected to the coding means, for converting the digital a i modulo m k integers into corresponding analog a l modulo m k signals; a plurality t of means for delaying the analog a i modulo m k integers, each means having an input connected to a D/A converting means, each delaying means having N outputs, h i mod m k ; a plurality t of means, connected to the delaying means, for summing the outputs of the delaying means; a plurality t of means, connected to the t summing means, for converting the analog a i modulo m k integers from the summing means into digital a i modulo m k integers; and means, connected to the t A/D converting means, for decoding the digital a i modulo m k numbers into a digital output, ##EQU6##