US4038688A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic low frequency gain limiting by addition method in video processing system
Assignee: United States Department of the Army
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Filing: 1976-01-19
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Granted: 1977-07-26
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Expires: 1996-01-19
Abstract
Abstract A low frequency gain limiting circuit for an AC coupled video processing tem wherein if the low frequency portion of video signals exceed a certain level, the low frequency pedestal is clipped and fed directly to a summing amplifier while simultaneously the low frequency pedestal is differentially compared in a differential amplifier with the original video signals and the resulting short pedestal with the high frequency detail remaining thereon is passed through a high pass filter before application of the high frequency detail only at a second input to the summing amplifier. The addition of the high frequency detail back onto the low frequency pedestal within the summing amplifier provides the gain limited video signal. A video signal comprising low frequency pedestals with amplitudes within the certain level are fed directly through the summing amplifier but no signal will be present at the output of the differential amplifier since both signals cancel.
Inventors
- 👤 Sen-Te Chow
- 👤 Earl M. Thomas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:28
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/20; H04N5/205
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
265 words
An automatic low frequency pedestal gain limiting circuit for composite video signals in an AC coupled video processing system, said gain limiting circuit comprising: a pedestal limiting circuit for clipping the low frequency pedestal voltages of said composite video signals into smoothly clipped pedestal voltages when said low frequency pedestal voltages exceed a pedestal limiting voltage level; a differential amplifier having first and second inputs and an output in which said composite video signals are applied at said first input to said differential amplifier and said smoothly clipped pedestal voltages are applied at said second input to said differential amplifier wherein said video signals and said smoothly clipped pedestal voltages are differentially compared by said differential amplifier to provide short pedestal voltages having the high frequency detail of said composite video signals remaining thereon at said output of said differential amplifier; a summing amplifier having first and second inputs and an output; means for removing said short pedestal voltages and passing said high frequency detail to said first input of said summing amplifier wherein said smoothly clipped pedestal voltages are also applied to said first input to said summing amplifier for summing said high frequency detail on said smoothly clipped pedestal voltages; and means for providing a reference voltage at said second input to said summing amplifier to sum with said high frequency detail on said smoothly clipped pedestal voltages to provide an output video signal therefrom that retains said high frequency detail thereon but limits the gain of the low frequency pedestals to maintain operation of said video processing system within its dynamic range.
Claim 2
Dependent Claim
265 words
An automatic low frequency pedestal gain limiting circuit for composite video signals in an AC coupled video processing system, said gain limiting circuit comprising: a pedestal limiting circuit for clipping the low frequency pedestal voltages of said composite video signals into smoothly clipped pedestal voltages when said low frequency pedestal voltages exceed a pedestal limiting voltage level; a differential amplifier having first and second inputs and an output in which said composite video signals are applied at said first input to said differential amplifier and said smoothly clipped pedestal voltages are applied at said second input to said differential amplifier wherein said video signals and said smoothly clipped pedestal voltages are differentially compared by said differential amplifier to provide short pedestal voltages having the high frequency detail of said composite video signals remaining thereon at said output of said differential amplifier; a summing amplifier having first and second inputs and an output; means for removing said short pedestal voltages and passing said high frequency detail to said first input of said summing amplifier wherein said smoothly clipped pedestal voltages are also applied to said first input to said summing amplifier for summing said high frequency detail on said smoothly clipped pedestal voltages; and means for providing a reference voltage at said second input to said summing amplifier to sum with said high frequency detail on said smoothly clipped pedestal voltages to provide an output video signal therefrom that retains said high frequency detail thereon but limits the gain of the low frequency pedestals to maintain operation of said video processing system within its dynamic range.
Claim 3
Dependent Claim
32 words
An automatic low frequency pedestal gain limiting circuit as set forth in claim 1 wherein said pedestal limiting circuit comprises back-to-back diodes connected in parallel between said composite video signals and ground.
Claim 4
Dependent Claim
57 words
An automatic low frequency pedestal gain limiting circuit as set forth in claim 2 wherein said means for removing said short pedestal voltages and passing said high frequency detail comprises a high pass filter and clipping circuit connected in parallel to ground between said output of said differential amplifier and said first input to said summing amplifier.
Claim 5
Dependent Claim
40 words
An automatic low frequency pedestal gain limiting circuit as set forth in claim 3 wherein said means for providing a reference voltage at said second input to said summing amplifier is a negative input connected through a resistor to ground.
Claim 6
Dependent Claim
47 words
An automatic low frequency pedestal gain limiting circuit as set forth in claim 4 wherein said high pass filter is a capacitor and resistor serially connected to ground and wherein said clipping circuit comprises back-to-back diodes connected in parallel with said resistor of said high pass filter.
Claim 7
Dependent Claim
70 words
An automatic low frequency pedestal gain limiting circuit as set forth in claim 2 wherein said means for providing a reference voltage at said second input to said summing amplifier comprises a differential circuit connected between said output of said differential amplifier and said second input to said summing amplifier for providing smooth sharply rounded shoulder voltages that approximates said short pedestal voltages at said output of said differential amplifier.
Claim 8
Dependent Claim
155 words
An automatic low frequency pedestal gain limiting circuit as set forth in claim 6 wherein said means for removing said short pedestal voltages and passing said high frequency detail comprises a direct connection through a resistor between said output of said differential amplifier and said first input to said summing amplifier for applying said short pedestal voltages having the high frequency detail thereon directly to said first input of said summing amplifier wherein said reference voltage at said second input to said summing amplifier which comprises said smooth sharply rounded shoulder voltages that approximates said short pedestal voltages having the high frequency detail thereon is subtracted from said short pedestal voltages having the high frequency detail thereon to provide an output video signal from said summing amplifier that retains said high frequency detail thereon but limits the gain of said short pedestal voltages to maintain operation of said video processing system within its dynamic range.
Claim 9
Dependent Claim
72 words
An automatic low frequency pedestal gain limiting circuit as set forth in claim 7 wherein said differential circuit more specifically comprises a resistor and capacitor wherein said resistor is connected in parallel with a clipping circuit comprising back-to-back diodes connected in parallel between said output of said differential amplifier and said second input to said summing amplifier and said capacitor is connected between said second input to said summing amplifier and ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-25 | 1981-01-24 | 1981-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-25 | 1985-01-24 | 1985-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-25 | 1989-01-24 | 1989-07-26 | $7700.00 | Window Closed / Lapsed |