← Back to Patent Explorer
US4038538A Expired / Lapsed US ⏱️ 0.0 years remaining

Integer and floating point to binary converter

Assignee: Unisys Corp
•
Filing: 1976-05-12
•
Granted: 1977-07-26
•
Expires: 1996-05-12
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract In a data processing system having a plurality of storage units, each unit therein storing in integer or normalized floating point format, an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, a converter transforms the stored data into pure binary values of selectively the same or the inverse relative order. To convert into the same relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical zero and the exponent is complemented if otherwise. Thereafter, the integer/fraction bit is complemented. To convert into the inverse relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical one and the exponent field is complemented if otherwise. Also, the integer/fraction field is complemented.

Inventors

  • 👤 Carl Frederick Semmelhaack
  • 👤 Mark Camillo Divecchio

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 11:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 178 words
A converter for use in a logic element storing a numerical digital value having an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, said converter comprising: controller means having a first and a second logical state for controlling conversion of said numerical digital value; means for complementing said exponent sign bit when both said integer/fraction sign bit equals a logical zero and said controller means is in said first logical state and when both said integer/fraction sign bit equals a logical one and said controller means is in said second logical state; means for complementing said exponent field when both said integer/fraction sign bit equals a logical one and said controller means is in said first logical state and when both said integer/fraction sign bit equals a logical zero and said controller means is in said second logical state; means for complementing said integer/fraction field when said controller means is in said second logical state; and means for complementing said integer/fraction bit when said controller means is in said first logical state.
Claim 2
Dependent Claim 178 words
A converter for use in a logic element storing a numerical digital value having an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, said converter comprising: controller means having a first and a second logical state for controlling conversion of said numerical digital value; means for complementing said exponent sign bit when both said integer/fraction sign bit equals a logical zero and said controller means is in said first logical state and when both said integer/fraction sign bit equals a logical one and said controller means is in said second logical state; means for complementing said exponent field when both said integer/fraction sign bit equals a logical one and said controller means is in said first logical state and when both said integer/fraction sign bit equals a logical zero and said controller means is in said second logical state; means for complementing said integer/fraction field when said controller means is in said second logical state; and means for complementing said integer/fraction bit when said controller means is in said first logical state.
Claim 3
Dependent Claim 159 words
A converter for use in a logic element storing a numerical digital value having an exponent sign bit, and an exponent field, an integer/fraction sign bit, and an integer/fraction field, said converter comprising: exclusive OR means having an output for combining in exclusive OR fashion the exponent sign bit with the complement of the integer/fraction sign bit and for like combining each bit individually of the exponent field with the integer/fraction sign bit and for outputting all results of said combining; control means having a first and a second logical state for controlling the conversion of said numerical digital value; complementing means coupled to the output of said exclusive OR means, the integer/fraction sign bit, and the integer/fraction field, said complementing means controlled by said control means for complementing each bit received when said control means is in its first logical state and for passing uncomplemented each bit received when said control means is in its second logical state.
Claim 4
Dependent Claim 159 words
A converter for use in a logic element storing a numerical digital value having an exponent sign bit, and an exponent field, an integer/fraction sign bit, and an integer/fraction field, said converter comprising: exclusive OR means having an output for combining in exclusive OR fashion the exponent sign bit with the complement of the integer/fraction sign bit and for like combining each bit individually of the exponent field with the integer/fraction sign bit and for outputting all results of said combining; control means having a first and a second logical state for controlling the conversion of said numerical digital value; complementing means coupled to the output of said exclusive OR means, the integer/fraction sign bit, and the integer/fraction field, said complementing means controlled by said control means for complementing each bit received when said control means is in its first logical state and for passing uncomplemented each bit received when said control means is in its second logical state.
Claim 5
Dependent Claim 195 words
A converter for use in a logic element storing a numerical digital value having an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, said converter comprising: control means having a first and a second logical state for controlling conversion of said variable digital value; a first exclusive OR circuit fed by said control means and by the integer/fraction sign bit; a second exclusive OR circuit fed by said first exclusive OR circuit and by each bit of the exponent field whereby each bit in the exponent field is combined in exclusive OR fashion with the output of said first exclusive OR circuit; an inverter circuit complementing the output of said first exclusive OR circuit; a third exclusive OR circuit fed by the exponent sign bit and by the output of said inverter circuit; and complementing means receiving the integer/fraction sign bit and each bit in the integer/fraction field, said complementing means being controlled by said control means for complementing each bit received when said complementing means is in its first logical state and for passing uncomplemented each bit received when said control means is in its second logical state.
Claim 6
Dependent Claim 195 words
A converter for use in a logic element storing a numerical digital value having an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, said converter comprising: control means having a first and a second logical state for controlling conversion of said variable digital value; a first exclusive OR circuit fed by said control means and by the integer/fraction sign bit; a second exclusive OR circuit fed by said first exclusive OR circuit and by each bit of the exponent field whereby each bit in the exponent field is combined in exclusive OR fashion with the output of said first exclusive OR circuit; an inverter circuit complementing the output of said first exclusive OR circuit; a third exclusive OR circuit fed by the exponent sign bit and by the output of said inverter circuit; and complementing means receiving the integer/fraction sign bit and each bit in the integer/fraction field, said complementing means being controlled by said control means for complementing each bit received when said complementing means is in its first logical state and for passing uncomplemented each bit received when said control means is in its second logical state.

References Cited (Backward Citations)

US3742198A Cited
US3961170A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-07-25 1981-01-24 1981-07-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-07-25 1985-01-24 1985-07-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-07-25 1989-01-24 1989-07-26 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag