Data clock separator with missing clock detect

Claim 3

b. triggering a second one-shot, in response to the detected condition, to generate a second timed pulse; c. activating an electronic switch in response to the second pulse; and d. using said switch to change the time constant value of the timing network of said window one-shot to thereby change the output pulse width of said window one-shot.

Claim 4

b. triggering a second one-shot, in response to the detected condition, to generate a second timed pulse; c. activating an electronic switch in response to the second pulse; and d. using said switch to change the time constant value of the timing network of said window one-shot to thereby change the output pulse width of said window one-shot.

Claim 11

The method of claim 4, wherein the time constant varying called for in step (g) comprises the application of current to the timing network of said window one-shot as a function of the charged state of said capacitor.

Claim 12

A signal analysis system wherein data signals are separated from clock signals in a received pulse train having pulse intervals alternately containing clock and data information, said system comprising: a window one-shot arranged to be triggered or retriggered to generate a time interval whenever either a data bit or a clock bit is presented to the system; an RC timing network for setting the duration of said time interval, said network including a trim resistor for precisely setting said duration; status means for indicating whether the last bit detected was a data bit or a clock bit; clock output means including a clock bit gate; data output means including a data bit gate; and means responsive to said window one-shot and said status means for generating a timed data bit gate actuation interval or a timed clock bit gate actuation interval for enabling the next bit detected on the received pulse train to be selectively coupled through either the clock bit gate or the data bit gate.

Claim 13

A signal analysis system wherein data signals are separated from clock signals in a received pulse train having pulse intervals alternately containing clock and data information, said system comprising: a window one-shot arranged to be triggered or retriggered to generate a time interval whenever either a data bit or a clock bit is presented to the system; an RC timing network for setting the duration of said time interval, said network including a trim resistor for precisely setting said duration; status means for indicating whether the last bit detected was a data bit or a clock bit; clock output means including a clock bit gate; data output means including a data bit gate; and means responsive to said window one-shot and said status means for generating a timed data bit gate actuation interval or a timed clock bit gate actuation interval for enabling the next bit detected on the received pulse train to be selectively coupled through either the clock bit gate or the data bit gate.

Claim 14

The signal analysis system of claim 6, further comprising bit shift compensation means for detecting the occurrence of a successive data or block bit in a time interval after an adjacent previous time interval that contained a clock or data bit, and for acting thereon to shorten the next time interval by decreasing the precisely set interval duration of said window one-shot by an amount small in comparison to the said duration, said bit shift compensation means comprising: a second one-shot having as one input the output of said window one-shot and as the other input the raw pulse train; an electronic switch actuated by said second one-shot; and a resistor coupled to the electronic switch such that when said switch is actuated by a second one-shot, the resistor is thereby added in parallel to the resistor of the RC timing network of said window one-shot to thereby shorten the time constant of this timing network and thus shorten the said interval duration.

Claim 15

The signal analysis system of claim 7 further comprising second bit shift compensation means comprising logical OR'ing means that OR the output of said window one-shot with the output of said second one-shot, to prevent the said data bit or said clock bit gate from closing due to a premature time-out of said window one-shot before a given clock or data bit has passed completely therethrough.

Claim 16

The bit shift compensation means of claim 8 wherein said electronic switch comprises a transistor switch.

Claim 17

The signal analysis system of claim 6 further comprising clock rate tracking means for varying the time interval of said window one-shot as a function of the average period of detected clock signals, said means comprising: pulse generation means for generating a pulse of a set pulse width in response to each detected clock signal; electronic switch means; capacitor means; means for normally changing the electrical charge on said capacitor means at a constant rate; and voltage-controlled current source means actuated as a function of the charge of said capacitor means, for coupling a current to the RC timing network of said window one-shot, said generated pulse actuating said electronic switch means to switchably counteract said means for changing the charge on said capacitor to enable the said capacitor means charge to thereby obtain a relatively constant value reflecting the average clock period.

Claim 18

The signal analysis system of claim 10 wherein the voltage-controlled current source means comprises a transistor biased to function in its active region.

Claim 19

The signal analysis system of claim 11 wherein the means for changing the charge on said capacitor means is a resistor coupled through a diode to a supply voltage such that said capacitor is charged thereby at a constant rate, except when said electronic switch is actuated, during which time said capacitor means discharges through said switch.

Claim 20

The signal analysis system of claim 6 wherein said status means comprises a 1st bit sensor that is normally set when a data bit has been coupled through the data bit gate and is normally reset when the next immediately-following clock bit is coupled through the clock bit gate.

Claim 21

The signal analysis system of claim 13 wherein said means responsive to said window one-shot and said status means comprises two exclusive OR logic gates wherein said last bit sensor inputs to one input of each of said gates and said window one-shot inputs its normal output to the first gate for creation of said clock bit gate actuation interval and its inverted output to the second gate for creation of said data bit gate actuation interval.

Claim 22

The signal analysis system of claim 14 wherein said status means further comprises phase detect means for differentiating between clock pulses and data pulses, said detector comprising: means for counting a plurality of data counts, said means being enabled only if no intervening clock counts are detected by the system, and being engaged to output a pulse when a specific count has been reached; and means for inhibiting the resetting of the last bit sensor when said specific count has been reached, so that said clock bit gate actuation interval, as inputted to said clock bit gate, remains active through the next time interval to allow the next pulse on the pulse train to be detected as a clock pulse rather than a data pulse.

Claim 23

The signal analysis system of claim 15 further comprising missing clock detect means, said means comprising: a missing clock one-shot; means for triggering said missing clock one-spot upon the concurrent occurrence of the indication by said last bit sensor that said last bit sensor has detected a data pulse and the timing out of said window one-shot; and means for outputting a signal reflecting the triggered state of said missing one-shot, wherein said means further acts to artificially emulate the reception of said last bit sensor of a clock bit, and acts to artificially trigger the said window one-shot to emulate the reception of a clock pulse.

Claim 26

The method of claim 17 wherein step (e) comprises the steps of: a. detecting from the status indicator that the last bit selected was a data bit; b. detecting the going-off of the window one-shot prior to the detection of a clock bit by the status indicator; and c. setting a missing clock one-shot in response thereto.

Claim 27

The method of claim 18 wherein step (g) comprises the steps of: a. resetting the status indicator by means of the missing clock one-shot such that said status indicator no longer indicates that the last bit detected was a data bit; and b. triggering the window one-shot by means of said missing clock one-shot to put said window one-shot in the state it would have been in had a clock pulse been detected by said window one-shot.

Claim 28

A signal analysis system wherein data signals are separated from clock signals in a received pulse train having pulse intervals alternatively containing clock and data information, said system comprising: a window one-shot arranged to be triggered or retriggered to generate a time interval whenever either a data pulse or a clock pulse is presented to the system; an RC timing network for setting the duration of said time interval, said network including a trim resistor for precisely setting said duration; status means for indicating whether the last pulse detected was a data pulse or a clock pulse; clock output means including a clock bit gate; data output means including a data bit gate; means responsive to said window one-shot and said status means for generating a timed data bit gate actuation interval or a timed clock bit gate actuation interval for enabling the next pulse detected on the received pulse train to be selectively coupled through either the clock bit gate or the data bit gate; bit shift compensation means for detecting successive pulses on the received pulse train and for shortening the time interval generated by said window one-shot in response thereto comprising means for switchably coupling a signal to said RC timing network for shortening thereby said network time constant; and clock rate tracking means for varying the time interval of said window one-shot as a function of the average period of clock pulses detected by said clock output means comprising a capacitor, means for controlling the charge on said capacitor as a function of said clock pulse period, and voltage-controlled current source means actuated as a function of the charge of said capacitor means, for coupling a current to said RC timing network of said window one-shot.

Claim 29

A signal analysis system wherein data signals are separated from clock signals in a received pulse train having pulse intervals alternatively containing clock and data information, said system comprising: a window one-shot arranged to be triggered or retriggered to generate a time interval whenever either a data pulse or a clock pulse is presented to the system; an RC timing network for setting the duration of said time interval, said network including a trim resistor for precisely setting said duration; status means for indicating whether the last pulse detected was a data pulse or a clock pulse; clock output means including a clock bit gate; data output means including a data bit gate; means responsive to said window one-shot and said status means for generating a timed data bit gate actuation interval or a timed clock bit gate actuation interval for enabling the next pulse detected on the received pulse train to be selectively coupled through either the clock bit gate or the data bit gate; bit shift compensation means for detecting successive pulses on the received pulse train and for shortening the time interval generated by said window one-shot in response thereto comprising means for switchably coupling a signal to said RC timing network for shortening thereby said network time constant; and clock rate tracking means for varying the time interval of said window one-shot as a function of the average period of clock pulses detected by said clock output means comprising a capacitor, means for controlling the charge on said capacitor as a function of said clock pulse period, and voltage-controlled current source means actuated as a function of the charge of said capacitor means, for coupling a current to said RC timing network of said window one-shot.