US4035666A
Expired / Lapsed
US
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Analogue shift register correlators
Assignee: Texas Instruments Inc
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Filing: 1975-10-08
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Granted: 1977-07-12
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Expires: 1995-10-08
Abstract
Abstract Semiconductor charge devices are defined to effect a serial-to-parallel conversion of analogue signal information. In one aspect of the invention, a digital signal is extracted from an analogue noise environment by a shift register correlator comprising a bucket-bridge configuration of field-effect transistors in combination with gating field-effect transistors which are effective to weight the amplitude of the data in corresponding bits of the shift register. The gates of the gating transistors are selectively connected to diffused regions of transistors of the bucket-brigade delay line to effect parallel tapped outputs therefrom. The weighted signals from the gating transistors are summed at a common terminal to form the auto-correlated output. In a different aspect of the invention, the analogue delay line is effected by a charge-coupled shift register, parallel taps being obtained from diffused regions under selected electrodes of the shift register ohmically connected to gates of the gating field-effect transistors.
Inventors
- 👤 Dean Robert Collins
- 👤 Lewis T. Clairborne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:05
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/04; G06; G06G; G06G7/00; G06G7/12; G06G7/19; G06G7/1907; H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/472; H10D44/476
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
249 words
A charge transfer device correlator comprising: (a) a semiconductor substrate; (b) a charge transfer device shift register having a plurality of successive stages defined adjacent one surface of said substrate, each said stage including a plurality of electrodes disposed on an insulating layer on said substrate surface; (c) means for applying clocking pulses to said electrodes for entering data samples into and propagating said data samples along said shift register; and (d) data sampling and amplitude weighting means for simultaneously detecting the data samples stored at each of said plurality of stages to produce a detected signal and for amplitude weighting said detected signals in a pre-selected manner, said data sampling and amplitude weighting means including a plurality of insulated gate field effect transistors respectively disposed adjacent said substrate surface adjacent a corresponding stage of said shift register, the gate electrodes of said plurality of transistors respectively connected to the corresponding stage of said shift register for detecting said data sample stored at that stage, each of said plurality of transistors defining a predetermined gain for weighting the amplitude of the detected signal produced by that transistor, source electrodes of each of said plurality of transistors commonly connected to the circuit ground; signal summation means; and insulated gate field effect transistor gating means connecting the drain electrodes of said first plurality of transistors to said signal summation means for transferring detected and weighted signals to said summation means in response to gating signals received by said transistor gating means.
Claim 2
Dependent Claim
249 words
A charge transfer device correlator comprising: (a) a semiconductor substrate; (b) a charge transfer device shift register having a plurality of successive stages defined adjacent one surface of said substrate, each said stage including a plurality of electrodes disposed on an insulating layer on said substrate surface; (c) means for applying clocking pulses to said electrodes for entering data samples into and propagating said data samples along said shift register; and (d) data sampling and amplitude weighting means for simultaneously detecting the data samples stored at each of said plurality of stages to produce a detected signal and for amplitude weighting said detected signals in a pre-selected manner, said data sampling and amplitude weighting means including a plurality of insulated gate field effect transistors respectively disposed adjacent said substrate surface adjacent a corresponding stage of said shift register, the gate electrodes of said plurality of transistors respectively connected to the corresponding stage of said shift register for detecting said data sample stored at that stage, each of said plurality of transistors defining a predetermined gain for weighting the amplitude of the detected signal produced by that transistor, source electrodes of each of said plurality of transistors commonly connected to the circuit ground; signal summation means; and insulated gate field effect transistor gating means connecting the drain electrodes of said first plurality of transistors to said signal summation means for transferring detected and weighted signals to said summation means in response to gating signals received by said transistor gating means.
Claim 3
Dependent Claim
17 words
A correlator according to claim 1, wherein said shift register is a charge coupled device shift register.
Claim 4
Dependent Claim
49 words
A correlator according to claim 2, further including a doped region in said substrate beneath an electrode of each stage of said shift register, and wherein the gates of said plurality of transistors are connected respectively to said doped regions for detecting the data samples stored at said stages.
References Cited (Backward Citations)
US3946247A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-11 | 1981-01-10 | 1981-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-11 | 1985-01-10 | 1985-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-11 | 1989-01-10 | 1989-07-12 | $7700.00 | Window Closed / Lapsed |