Cardiotachometer

Claim 2

A cardiotachometer comprising: a sensor responsive to an ECG signal to provide a pulse train representing heart beats, a clock providing a timing signal once each n seconds, counting means responsive to said pulse train and to said timing signal to provide a count of the number of said pulses in said pulse train each n second time period, there being m of said time periods in sixty seconds, `intermediate storage means coupled to the output of said counter means and to said timing signal to provide a count of the number of pulses in said pulse train during m successive n second time periods, updating means coupled to said timing signal and to said intermediate storage means to update the count held by said intermediate storage once each n seconds, a p bit output storage means, multiplexer means having a first and second state, said multiplexer means when in said first state interfacing between said counter and the upper bits of said output storage means, said multiplexer means when in said second state interfacing between said intermediate storage means and said output storage means, and latching means having a first state output signal and a second state output signal, said first state output signal of said latching means forcing said multiplexer into its first state and said second state output signal from said latching means forcing said multiplexer into its second state, said latching means being responsive to said timing signals to be switched into its second state in response to the mth one of said timing signals after said clock is initially turned on, said timing signal being coupled to said output storage means to update said output storage means once each n seconds.

Claim 3

The cardiotachometer of claim 1, wherein: said n second time period is 15 seconds, and said multiplexer when in said first state interfacing between said counter and the upper p-2 bits of said output storage means.

Claim 4

The cardiotachometer of claim 2 wherein: said intermediate storage means and said output storage means are registers.

Claim 5

The cardiotachometer of claim 3 wherein: said clock is responsive to a first heart beat signal from said ECG signal to be turned on by said first heart beat signal.

Claim 6

The cardiotachometer of claim 4 further comprising: means responsive to the turning on of the cardiotachometer to provide a turn-on signal, said counting means and said clock being reset to zero by said turn-on signal and said latching means being switched into said first state by said turn-on signal.

Claim 7

The cardiotachometer of claim 3 further comprising: means responsive to the turning on of the cardiotachometer to provide a turn-on signal, said counting means being reset by said turn-on signal and said latching means being switched into said first state by said turn-on signal.

Claim 8

The cardiotachometer of claim 2 wherein: said clock is responsive to a first heart beat signal from said ECG signal to be turned on by said first heart beat signal.

Claim 9

The cardiotachometer of claim 2 further comprising: means responsive to the turning on of the cardiotachometer to provide a turn-on signal, said counting means being reset by said turn-on signal and said latching means being switched into said first state by said turn-on signal.

Claim 10

The cardiotachometer of claim 1 wherein: said intermediate storage means and said output storage means are registers.

Claim 11

The cardiotachometer of claim 1 wherein: said clock is responsive to a first heart beat signal from said ECG signal to be turned on by said first heart beat signal.

Claim 12

The cardiotachometer of claim 1 further comprising: means responsive to the turning on of the cardiotachometer to provide a turn-on signal, said counting means being reset by said turn-on signal and said latching means being switched into said first state by said turn-on signal.

Claim 13

A cardiotachometer comprising: sensing means responsive to an ECG signal to provide a pulse train representing heart beats, a six bit counter responsive to said pulse train to provide a count of the number of pulses in said train, a clock providing a timing pulse once each 15 seconds, first, second, third and fourth intermediate registers connected in tandem, the output of said counter being connected to the input of said intermediate register, the output of said first intermediate register being coupled to the input of said second intermediate register, the output of said second intermediate register being coupled to the input of said third intermediate register and the output of said third intermediate register being coupled to the input of said fourth intermediate register, an adder connected to the output of said four intermediate registers to provide a sum output value equal to the sum of the values held in said four intermediate registers, timing generator means responsive to each of said timing pulses to provide a set of six successive sequencing pulses, the first four of said sequencing pulses being coupled respectively to said fourth, third, second and first intermediate registers, to sequentially load the content of said third intermediate register into said fourth intermediate register, load the content of said second intermediate register into said third intermediate register, load the content of said first intermediate register into said second intermediate register and load the content of said counter into said first intermediate register, an eight bit output register, multiplexer means between the output of said counter and said output register, said multiplexer means also being between the output of said adder and said output register, said multiplexer having a first state in which the output of said counter is applied to the upper six bits of said output register and a second state in which the output of said adder is applied to said output register, latching means responsive to said timing pulses to force said multiplexer into said first state upon generation of the first of said timing pulses after turn-on of said clock and to force said multiplexer into said second state upon generation of the fourth of said timing pulses after turn-on of said clock, the fifth of said sequencing pulses coupled to said output register to load said output register once every 15 seconds, the sixth of said sequencing pulses coupled to said counter to reset said counter once every 15 seconds, and display means responsive to said output register to provide a visual reading representing the value stored in said output register.

Claim 14

A cardiotachometer comprising: sensing means responsive to an ECG signal to provide a pulse train representing heart beats, a six bit counter responsive to said pulse train to provide a count of the number of pulses in said train, a clock providing a timing pulse once each 15 seconds, first, second, third and fourth intermediate registers connected in tandem, the output of said counter being connected to the input of said intermediate register, the output of said first intermediate register being coupled to the input of said second intermediate register, the output of said second intermediate register being coupled to the input of said third intermediate register and the output of said third intermediate register being coupled to the input of said fourth intermediate register, an adder connected to the output of said four intermediate registers to provide a sum output value equal to the sum of the values held in said four intermediate registers, timing generator means responsive to each of said timing pulses to provide a set of six successive sequencing pulses, the first four of said sequencing pulses being coupled respectively to said fourth, third, second and first intermediate registers, to sequentially load the content of said third intermediate register into said fourth intermediate register, load the content of said second intermediate register into said third intermediate register, load the content of said first intermediate register into said second intermediate register and load the content of said counter into said first intermediate register, an eight bit output register, multiplexer means between the output of said counter and said output register, said multiplexer means also being between the output of said adder and said output register, said multiplexer having a first state in which the output of said counter is applied to the upper six bits of said output register and a second state in which the output of said adder is applied to said output register, latching means responsive to said timing pulses to force said multiplexer into said first state upon generation of the first of said timing pulses after turn-on of said clock and to force said multiplexer into said second state upon generation of the fourth of said timing pulses after turn-on of said clock, the fifth of said sequencing pulses coupled to said output register to load said output register once every 15 seconds, the sixth of said sequencing pulses coupled to said counter to reset said counter once every 15 seconds, and display means responsive to said output register to provide a visual reading representing the value stored in said output register.

Claim 15

The cardiotachometer of claim 12 wherein: said clock is responsive to a first heart beat signal from said ECG signal to be turned on by said first heart beat signal.

Claim 16

The cardiotachometer of claim 13 further comprising: means responsive to the turning on of the cardiotachometer to provide a turn-on signal, said counter and said clock means being reset to zero by said turn-on signal and said latching means being switched into said first state by said turn-on signal.

Claim 17

The cardiotachometer of claim 12 further comprising: means responsive to the turning on of the cardiotachometer to provide a turn-on signal, said counter being reset by said turn-on signal and said latching means being switched into said first state by said turn-on signal.