Complementary symmetry fet mixer circuits

Claim 2

A mixer circuit comprising, in combination: two terminals between which an operating voltage may be applied; two field effect transistors of complementary conductivity types, each having an input electrode, an output electrode, a conduction path between these electrodes, and a control electrode, said two paths being connected to one another at their output electrodes, and said two paths being connected in series between said terminals; means for quiescently biasing both control electrodes to quiescently operate both transistors in the linear region of their operating range; means for applying a signal at a frequency f 1 between the control and input electrodes of said first transistor; means for applying a signal at a frequency f 2 between the control and input electrodes of said second transistor; and a circuit output terminal connected to said output electrodes for supplying signals at a sum frequency (f 1 + f 2 ) and a difference frequency (f 1 - f 2 ).

Claim 3

A mixer circuit as set forth in claim 1, wherein said means for applying a signal at frequency f 1 comprises a parallel resonant circuit tuned to frequency f 1 , and wherein said means for applying a signal at frequency f 2 comprises a parallel resonant circuit tuned to frequency f 2 .

Claim 4

A mixer circuit as set forth in claim 1, further including a resonant circuit tuned to one of the frequencies (f 1 + f 2 ) and (f 1 - f 2 ) connected between said output terminal and another circuit point.

Claim 5

A mixer circuit as set forth in claim 3, wherein said resonant circuit comprises a parallel resonant circuit, said other circuit point comprising a point at a reference potential.

Claim 6

A mixer circuit as set forth in claim 3, wherein said resonant circuit comprises a series resonant circuit, said other circuit point comprising a point at a reference potential and further including a point on said series resonant circuit to which the control electrode of another field effect transistor may be connected.

Claim 7

A mixer circuit comprising, in combination: two terminals between which an operating voltage may be applied, both grounded with respect to the frequencies f 1 and f 2 of interest; a P-type MOS transistor and an N-type MOS transistor, each having source, drain and gate electrodes, and a conduction path between the source and drain electrode, the drain electrodes of said transistors each being connected at a common terminal, and said conduction paths being connected in series between said terminals; means for quiescently biasing said transistor to operate in the linear region of their operating characteristic; a parallel resonant circuit tuned to frequency f 1 coupled between the source and gate electrodes of said N-type transistor; first input means coupled to said parallel resonant circuit for supplying an input signal at frequency f 1 to said parallel resonant circuit; a second parallel resonant circuit, this one tuned to frequency f 2 , coupled between the source and gate electrodes of said P-type transistor; second input means coupled to said second parallel resonant circuit for supplying an input signal at frequency f 2 to said second parallel resonant circuit; an output terminal connected to said common terminal for supplying signals at a sum frequency (f 1 + f 2 ) and a difference frequency (f 1 - f 2 ); and an output circuit tuned to one of the sideband frequencies of f 1 + f 2 and f 1 - f 2 coupled between said output terminal and a second circuit point.

Claim 8

A mixer circuit comprising, in combination: two terminals between which an operating voltage may be applied, both grounded with respect to the frequencies f 1 and f 2 of interest; a P-type MOS transistor and an N-type MOS transistor, each having source, drain and gate electrodes, and a conduction path between the source and drain electrode, the drain electrodes of said transistors each being connected at a common terminal, and said conduction paths being connected in series between said terminals; means for quiescently biasing said transistor to operate in the linear region of their operating characteristic; a parallel resonant circuit tuned to frequency f 1 coupled between the source and gate electrodes of said N-type transistor; first input means coupled to said parallel resonant circuit for supplying an input signal at frequency f 1 to said parallel resonant circuit; a second parallel resonant circuit, this one tuned to frequency f 2 , coupled between the source and gate electrodes of said P-type transistor; second input means coupled to said second parallel resonant circuit for supplying an input signal at frequency f 2 to said second parallel resonant circuit; an output terminal connected to said common terminal for supplying signals at a sum frequency (f 1 + f 2 ) and a difference frequency (f 1 - f 2 ); and an output circuit tuned to one of the sideband frequencies of f 1 + f 2 and f 1 - f 2 coupled between said output terminal and a second circuit point.

Claim 9

A mixer circuit comprising, in combination: two terminals between which an operating voltage may be applied; four field effect transistors, the first and second of said transistors are of a first conductivity type and the third and fourth of which are of a second conductivity type complementary to the first conductivity type, each transistor having an input electrode, an output electrode and a control electrode, and each having a conduction path between its input and output electrodes, the conduction paths of said first and third transistors being connected in series between said terminals, the conduction paths of said second and fourth transistors being connected in series between said terminals in the same way as said first and third transistors, the output electrodes of said first and third transistors being connected at a first interconnection, the output electrodes of said second and fourth electrodes being connected at a second interconnection; means for quiescently biasing all of said transistors to operate in the linear region of their operating range; means for applying a signal of frequency f 1 , in one phase to the control electrode of said first transistor and in opposite phase to the control electrode of said second transistor; means for applying a signal of frequency f 2 to the control electrodes of said third and fourth transistors; first and second output terminals respectively connected to said first and second interconnections for supplying between said first and second output terminals signals at a sum frequency (f 1 + f 2 ) and a difference frequency (f 1 - f 2 ); and an output circuit tuned to one of the sideband frequencies f 1 + f 2 and f 1 - f 2 connected between said first and second output terminals.

Claim 10

A mixer circuit comprising, in combination: two terminals between which an operating voltage may be applied; four field effect transistors, the first and second of said transistors are of a first conductivity type and the third and fourth of which are of a second conductivity type complementary to the first conductivity type, each transistor having an input electrode, an output electrode and a control electrode, and each having a conduction path between its input and output electrodes, the conduction paths of said first and third transistors being connected in series between said terminals, the conduction paths of said second and fourth transistors being connected in series between said terminals in the same way as said first and third transistors, the output electrodes of said first and third transistors being connected at a first interconnection, the output electrodes of said second and fourth electrodes being connected at a second interconnection; means for quiescently biasing all of said transistors to operate in the linear region of their operating range; means for applying a signal of frequency f 1 , in one phase to the control electrode of said first transistor and in opposite phase to the control electrode of said second transistor; means for applying a signal of frequency f 2 to the control electrodes of said third and fourth transistors; first and second output terminals respectively connected to said first and second interconnections for supplying between said first and second output terminals signals at a sum frequency (f 1 + f 2 ) and a difference frequency (f 1 - f 2 ); and an output circuit tuned to one of the sideband frequencies f 1 + f 2 and f 1 - f 2 connected between said first and second output terminals.

Claim 11

A mixer circuit as set forth in claim 7, wherein said means for applying a signal of frequency f 2 comprises means for applying said signal in the same phase to the control electrodes of the third and fourth transistors.

Claim 12

A mixer circuit as set forth in claim 7, wherein said means for applying a signal at frequency f 2 comprises means for applying said signal in one phase to the control electrode of the third transistor and in opposite phase to the control electrode of the fourth of said transistors.