Four-wire integrable hybrid

Claim 2

In a port circuit for a time-sampled switching system having a low-pass filter, the combination comprising: a first high input impedance transmission path including means for periodically passively sampling voltages transmitted through said filter in one direction; and a second transmission path having low output impedance coupled to said filter for applying thereto discrete current impulses at intervals substantially equal to the reciprocal of twice the cut-off frequency of said filter.

Claim 3

In a port circuit for a time-sampled switching system having a low-pass filter including a final shunt capacitor, the combination comprising: a first transmission path presenting a high input impedance to time varying signals traversing said filter in a first direction, said first path including a sampling capacitor and means for periodically applying an amplitude fraction of said signals to said sampling capacitor; and a second transmission path periodically presenting a low driving point impedance to said filter, said second path including means for periodically impulse charging said final shunt capacitor of said filter to force signals therethrough in a direction opposite to said first direction.

Claim 4

In a port circuit for a time-sampled switching system having a low-pass filter including a final shunt capacitor, the combination comprising: a first transmission path presenting a high input impedance to time varying signals traversing said filter in a first direction, said first path including a sampling capacitor and means for periodically applying an amplitude fraction of said signals to said sampling capacitor; and a second transmission path periodically presenting a low driving point impedance to said filter, said second path including means for periodically impulse charging said final shunt capacitor of said filter to force signals therethrough in a direction opposite to said first direction.

Claim 5

An integrated solid state electronic circuit comprising: a bidirectional transmission terminal and a first and second unidirectional transmission terminal, a send and a receive strobe clock terminal and a send and a receive ramp terminal; a first, second and third gated signal switch and a signal comparator each having an input, an output and a control terminal, the input terminal of said first and the output terminal of said second gated signal switch being connected together at said bidirectional transmission terminal; means connecting the output terminal of said first gated signal switch to the input terminal of said comparator; means connecting the output terminal of said comparator to said first unidirectional transmission terminal; means connecting the control terminal of said comparator to said send ramp terminal; means connecting the control terminal of said third gated signal switch to said second unidirectional transmission terminal; means connecting the input terminal of said third gated signal switch to said receive ramp terminal; means connecting the output terminal of said third gated signal switch to the input terminal of said second gated input switch; and means respectively connecting the control terminals of said first and said second gated signal switches to said send and to said receive strobe clock terminals.

Claim 6

An integrated solid state electronic circuit comprising: a bidirectional transmission terminal and a first and second unidirectional transmission terminal, a send and a receive strobe clock terminal and a send and a receive ramp terminal; a first, second and third gated signal switch and a signal comparator each having an input, an output and a control terminal, the input terminal of said first and the output terminal of said second gated signal switch being connected together at said bidirectional transmission terminal; means connecting the output terminal of said first gated signal switch to the input terminal of said comparator; means connecting the output terminal of said comparator to said first unidirectional transmission terminal; means connecting the control terminal of said comparator to said send ramp terminal; means connecting the control terminal of said third gated signal switch to said second unidirectional transmission terminal; means connecting the input terminal of said third gated signal switch to said receive ramp terminal; means connecting the output terminal of said third gated signal switch to the input terminal of said second gated input switch; and means respectively connecting the control terminals of said first and said second gated signal switches to said send and to said receive strobe clock terminals.

Claim 7

In combination with the integrated solid state electronic circuit of claim 3 a first sampling capacitor connected at the output terminal of said first gated signal switch, and a said second sampling capacitor connected at the input terminal of said second gated signal switch.

Claim 8

In combination with the circuit as defined in claim 4, a port circuit having a low-pass filter including a final shunt capacitor connected to said bidirectional transmission terminal.

Claim 9

The invention of claim 5 wherein said first sampling capacitor is substantially smaller than said final shunt capacitor of said low-pass filter.

Claim 10

In a time sampled switching system including a port circuit having a bidirectional transmission terminal connected to a low-pass filter and a pair of unidirectional transmission terminals, the combination comprising: a first transmission path including a gated signal switch interposed between said bidirectional terminal and a first of said unidirectional terminals, said first transmission path including a gated signal switch, a first sampling capacitor and a comparator; a second transmission path interposed between said bidirectional terminal and the second of unidirectional terminals, said second transmission path including a pair of serially-connected gated signal switches and a second sampling capacitor in shunt with the input of one and the output of the other of the gated signal switches in said second path.

Claim 11

In a time sampled switching system including a port circuit having a bidirectional transmission terminal connected to a low-pass filter and a pair of unidirectional transmission terminals, the combination comprising: a first transmission path including a gated signal switch interposed between said bidirectional terminal and a first of said unidirectional terminals, said first transmission path including a gated signal switch, a first sampling capacitor and a comparator; a second transmission path interposed between said bidirectional terminal and the second of unidirectional terminals, said second transmission path including a pair of serially-connected gated signal switches and a second sampling capacitor in shunt with the input of one and the output of the other of the gated signal switches in said second path.

Claim 12

The invention of claim 7 further comprising means for applying a send ramp waveform to said comparator, and means for applying a receive ramp waveform to one of the gated signal switches in said second transmission path.

Claim 13

The combination of claim 8 wherein said means for applying said receive ramp waveform to said gated signal switch applies a waveform having a steeper amplitude-per-unit-time slope than the slope of the waveform applied by said means for applying said send ramp waveform to said comparator.

Claim 14

The invention of claim 9 wherein the onset of said receive ramp waveform applied to said gated signal switch is delayed by a predetermined interval of time from the onset of the transmit ramp waveform applied to said comparator.

Claim 15

In a time sampled switching system including a port circuit having a bidirectional transmission terminal connected to a low-pass filter including a final shunt capacitor, the combination comprising: a first and a second sampling capacitor, means for sampling the voltage on said first sampling capacitor and for applying to said final shunt capacitor a current impulse sufficient to bring the voltage thereon to that of said first sampling capacitor, and means thereafter operative following a delay interval equal to an odd multiple of half cycles measured at the cutoff frequency of said filter for sampling the voltage on said final shunt capacitor and for applying a corresponding voltage to said second sampling capacitor.

Claim 16

In a time sampled switching system including a port circuit having a bidirectional transmission terminal connected to a low-pass filter including a final shunt capacitor, the combination comprising: a first and a second sampling capacitor, means for sampling the voltage on said first sampling capacitor and for applying to said final shunt capacitor a current impulse sufficient to bring the voltage thereon to that of said first sampling capacitor, and means thereafter operative following a delay interval equal to an odd multiple of half cycles measured at the cutoff frequency of said filter for sampling the voltage on said final shunt capacitor and for applying a corresponding voltage to said second sampling capacitor.

Claim 17

The invention of claim 11 further comprising a current source; said means for sampling said voltage on said first capacitor and for applying said current impulse to said final shunt capacitor including means for charging said shunt capacitor from said current source.

Claim 18

The invention of claim 12 further comprising a source of ramp signals; a pair of unidirectional transmission terminals; means for receiving a duration-encoded signal on the first of said terminals and for applying a charge to said first sampling capacitor proportional to the duration of said signal; and means for comparing the voltage on said second sampling capacitor with said ramp signal for applying a duration-coded signal to the second of said unidirectional terminals corresponding to said second capacitor voltage.