Method of manufacturing dielectrically isolated semiconductive device

Claim 3

The method of claim 1, wherein: the first set of parallel regions is formed by etching only partially through the epitaxial layer in the thickness direction to form a first set of grooved regions in the epitaxial layer and then growing an oxide of the wafer material in the grooved regions to a depth sufficient to form an oxide region extending completely through the epitaxial layer.

Claim 4

The method of claim 2 wherein: the islands are formed by growing an oxide of the wafer material in parallel regions of the epitaxial layer crossing the grooved regions to a depth less than the thickness of the epitaxial layer simultaneously with the growing of an oxide in the grooved regions.

Claim 7

The method of claim 4 wherein the steps of forming the first and second sets of insulating oxide regions comprises the steps of: depositing a silicon nitride layer on the epitaxial layer; forming a first patterned layer of masking material on the silicon nitride layer to define a first set of parallel exposed regions of silicon nitride; etching through said first set of exposed regions of silicon nitride to produce a corresponding first set of parallel exposed regions of said epitaxial layer; removing the first patterned layer of masking material; etching partially through said exposed regions of epitaxial layer to form a set of parallel grooved regions therein; forming a second patterned layer of masking material on both the silicon nitride layer and the exposed grooved regions of the epitaxial layer to define a second set of parallel exposed regions of silicon nitride crossing said set of parallel grooved regions in said epitaxial layer; etching through said second set of exposed regions of silicon nitride to produce a corresponding second set of parallel exposed regions of epitaxial layer; removing said layer of masking material to expose said set of parallel grooved regions; growing first and second sets of insulating oxide regions in said set of parallel grooved regions and said second set of parallel exposed regions of said epitaxial layer, respectively, to a depth such that each of said first set of insulating oxide regions extends completely through said epitaxial layer and each of said second set of insulating oxide regions extends only partially through said epitaxial layer; and removing said layer of silicon nitride to expose individual regions of said epitaxial layer isolated by said insulating oxide regions.

Claim 8

The method of claim 5 wherein the step of converting the epitaxial layer comprises the steps of: subjecting the etched wafer to a Boron Tribromide diffusion at a temperature of about 1000° C.; using nitrogen as a primary carrier flowing at the rate of approximately 3000 cc per minute and oxygen flowing at a rate of about 20 cc per minute.

Claim 9

The method of claim 6 wherein the step of forming ohmic connections comprises the steps of: forming a layer of oxide material over the converted epitaxial layer and the grooves; etching contact holes in the layer of oxide in alignment with each of the islands; and forming a metallic line on the oxide layer and in the contact holes in ohmic contact with corresponding islands in each row.