Static inverter control circuit

Claim 2

In a complementary impulse commutated inverter circuit of the type including first and second controllable switching means connected in alternate load current carrying paths between a DC power source and an inductive load, an improved control circuit including means for producing gating signals having a predetermined normal time duration, said control circuit having first and second output terminals and an input terminal, said first and second output terminals being connected to control terminals of said controllable switch means, said input terminal being connected to receive an inverter enable command signal said control circuit comprising: a. means responsive to said enable command signal for initially supplying a first gating signal to a predetermined one of said controllable switching means and for thereafter supplying subsequent gating signals alternately to both of said controllable switching means; b. means responsive to the removal of said enable command signal for causing a last gating signal to be applied to said predetermined one of said controllable switching means; and c. means for prematurely terminating said last gating signal so that said last gating signal is of a subnormal duration.

Claim 3

The invention as defined in claim 1 wherein termination of said gating signals is accomplished such that the last gating signal is of a time duration shorter than that required after receipt of said last gating signal for current reversal in said load.

Claim 4

A control circuit for a complementary impulse commutated inverter of the type including first and second controllable switching means arranged respectively in first and second alternate load current conduction paths between a source of DC power and an inductive load, commutating circuit components being connected to each of said controllable switching means, said control circuit comprising: a. first and second oscillators connected respectively to alternately supply gating signals to said first and second controllable switching means, conduction of said first controllable switching means occuring in a first half-cycle and conduction of said second controllable switching means occuring in a second half-cycle; b. a logic circuit connected to receive inverter enable commands and arranged to supply said enable commands to said first and second oscillators in a manner to always start inverter operation by first gating said first controllable switching means followed by alternate gating of both of said controllable switching means, said logic circuit also being connected to respond to an inverter disable command by gating said first controllable switching means for a time interval sufficient to assure commutation of the second controllable switching means, said time interval being sufficiently short to allow self-commutation of said first controllable switching means, thereby terminating inverter operation only at the end of the half-cycle in which the second controllable switching means was last conducting load current.

Claim 5

A control circuit for a complementary impulse commutated inverter of the type including first and second controllable switching means arranged respectively in first and second alternate load current conduction paths between a source of DC power and an inductive load, commutating circuit components being connected to each of said controllable switching means, said control circuit comprising: a. first and second oscillators connected respectively to alternately supply gating signals to said first and second controllable switching means, conduction of said first controllable switching means occuring in a first half-cycle and conduction of said second controllable switching means occuring in a second half-cycle; b. a logic circuit connected to receive inverter enable commands and arranged to supply said enable commands to said first and second oscillators in a manner to always start inverter operation by first gating said first controllable switching means followed by alternate gating of both of said controllable switching means, said logic circuit also being connected to respond to an inverter disable command by gating said first controllable switching means for a time interval sufficient to assure commutation of the second controllable switching means, said time interval being sufficiently short to allow self-commutation of said first controllable switching means, thereby terminating inverter operation only at the end of the half-cycle in which the second controllable switching means was last conducting load current.