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US4028150A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making reliable MOSFET device

Assignee: International Business Machines Corp
•
Filing: 1976-02-09
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Granted: 1977-06-07
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Expires: 1996-02-09
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Abstract

Abstract A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by providing a thin film of phosphosilicate glass (PSG) on the thin dielectric and completely covering the PSG layer with the gate metallization. The metallization extends over a thick film of phosphosilicate glass which is disposed on the thick insulator covering the source and drain regions.

Inventors

  • 👤 Robert Henry Collins
  • 👤 Richard F. Levine
  • 👤 William D. North
  • 👤 Gerald D. O'Rourke
  • 👤 Gerald R. Parker

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 21:41
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 166 words
A method for fabricating a field effect transistor, in which the active regions of the transistor are protected against contamination, comprising the steps of: forming a silicon dioxide coating on a surface of a silicon semiconductor substrate; removing portions of said coating to expose spaced adjacent regions in the substrate; depositing phosphorus pentoxide on the oxide coating and on said exposed regions; heating the substrate in an oxygen atmosphere to cause phosphorus to diffuse into said exposed adjacent regions, thereby forming source and drain regions of a field effect transisitor, and also a relatively thick composite insulator layer, over said exposed source and drain regions, of silicon dioxide and phosphosilicate glass; exposing a channel region between said source and drain regions; forming a thin coating of silicon dioxide over said exposed channel region; forming a thin layer of phosphosilicate glass on said thin oxide; and depositing a gate electrode over said thin layer of phosphosilicate glass and over a portion of said thick composite insulator layer.
Claim 2
Independent Claim 166 words
A method for fabricating a field effect transistor, in which the active regions of the transistor are protected against contamination, comprising the steps of: forming a silicon dioxide coating on a surface of a silicon semiconductor substrate; removing portions of said coating to expose spaced adjacent regions in the substrate; depositing phosphorus pentoxide on the oxide coating and on said exposed regions; heating the substrate in an oxygen atmosphere to cause phosphorus to diffuse into said exposed adjacent regions, thereby forming source and drain regions of a field effect transisitor, and also a relatively thick composite insulator layer, over said exposed source and drain regions, of silicon dioxide and phosphosilicate glass; exposing a channel region between said source and drain regions; forming a thin coating of silicon dioxide over said exposed channel region; forming a thin layer of phosphosilicate glass on said thin oxide; and depositing a gate electrode over said thin layer of phosphosilicate glass and over a portion of said thick composite insulator layer.
Claim 3
Dependent Claim 24 words
A method as in claim 1 wherein the steps of forming of said silicon oxide coatings comprise thermally growing said oxide from said body.
Claim 4
Independent Claim 152 words
A method for fabricating a field effect transistor, in wich the active regions of the transistor are protected against contamination, comprising the steps of: forming a silicon dioxide coating on a surface of a silicon semiconductor substrate; removing portions of said coating to expose spaced adjacent regions in the substrate; depositing a conductivity determining dopant in said regions, thereby forming source and drain regions of said field effect transisitors; reforming a relatively thick layer of silicon dioxide over said source and drain regions; forming a relatively thick layer of phosphosilicate glass over said thick insulator layer; exposing a channel region between said source and drain regions; forming a thin coating of silicon dioxide over said exposed channel region; forming a thin layer of phosphosilicate glass on said thin oxide; and depositing a gate electrode over said thin layer of phosphosilicate glass and over a portion of said thick layer of phosphosilicate glass.
Claim 5
Independent Claim 152 words
A method for fabricating a field effect transistor, in wich the active regions of the transistor are protected against contamination, comprising the steps of: forming a silicon dioxide coating on a surface of a silicon semiconductor substrate; removing portions of said coating to expose spaced adjacent regions in the substrate; depositing a conductivity determining dopant in said regions, thereby forming source and drain regions of said field effect transisitors; reforming a relatively thick layer of silicon dioxide over said source and drain regions; forming a relatively thick layer of phosphosilicate glass over said thick insulator layer; exposing a channel region between said source and drain regions; forming a thin coating of silicon dioxide over said exposed channel region; forming a thin layer of phosphosilicate glass on said thin oxide; and depositing a gate electrode over said thin layer of phosphosilicate glass and over a portion of said thick layer of phosphosilicate glass.
Claim 6
Dependent Claim 53 words
A method as in claim 3 wherein said thick insulator layer is silicon dioxide and wherein the forming of the thick and thin phosphosilicate glass layers is accomplished by heating the semiconductor substrate in an atmosphere containing phosphorus oxychloride and oxygen, thereby depositing phosphorus pentoxide on the surface of the silicon dioxide layers.

References Cited (Backward Citations)

US3300339A Cited
US3343049A Cited
US3507716A Cited
US3476619A Cited
US3497407A Cited
US3512057A Cited
US3560810A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-06-06 1980-12-06 1981-06-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-06-06 1984-12-06 1985-06-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-06-06 1988-12-06 1989-06-07 $7700.00 Window Closed / Lapsed

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