Frequency domain automatic equalizer having logic circuitry

Claim 2

A frequency domain equalizer for automatically equalizing the spectral components of a received signal transmitted through a distortion affected transmission channel comprising: (a) multiplying means for performing a complex multiplication of a complex input signal X and a complex multiplicand correction signal C, said multiplying means generating a complex product signal Y, said input signal X having a first factor, D, corresponding to a distortion transfer function of said transmission channel, and a second factor, H, corresponding to an undistorted transfer function of said transmission channel; (b) feedback control means receiving said complex product signal Y for generating a value of said correction signal C which is approximately inversely proportional to said first factor D of said multiplier input signal X; (c) said feedback control means comprising: (1) reference means for generating a complex reference signal proportional to said second factor, H, of said input signal X; (2) means for comparing said product signal Y with said reference signal; (3) means for generating error signals having an algebraic sign corresponding to the difference between said compared product signal Y and said reference signal; (4) means for adjusting the value of said correction signal C to produce a value for said product signal Y approximately equal to said reference signal; and (5) said adjusting means responsive to the algebraic sign of said error signals and the algebraic sign of real and imaginary components of said input signal X.

Claim 3

A frequency domain equalizer as recited in claim 1 wherein said adjusting means comprises: (a) reversible counter means for generating values of said correction signals C and (b) steering logic means responsive to the algebraic sign of said error signals and the algebraic sign of real and imaginary components of said input signal X for incrementing and decrementing said reversible counter means.

Claim 4

A frequency domain equalizer as recited in claim 2 wherein said steering logic means is responsive solely to the algebraic sign of said error signals and the algebraic sign of the real and imaginary components of said input signal X.

Claim 5

A frequency domain equalizer as recited in claim 2 further comprising means for detecting the algebraic sign of said error signals and said real and imaginary components of said input signal X.

Claim 6

A frequency domain equalizer as recited in claim 4 wherein said sign detecting means comprises slicing circuits.

Claim 7

A frequency domain equalizer as recited in claim 4 wherein said sign detecting means has a deadband at a zero level.

Claim 8

A frequency domain equalizer as recited in claim 1 wherein said multiplying means and said feedback control means are operable for a plurality of complex spectral components X n , where X n is any given component of said input signal and n is an integer.

Claim 9

A frequency domain equalizer as recited in claim 7 wherein a single feedback control means is time shared by at least one of said channels n.

Claim 10

A frequency domain equalizer as recited in claim 8 wherein said multiplying means comprises a plurality of separate multipliers and at least some of said multipliers are time shared together with said feedback control means.

Claim 11

A frequency domain equalizer as recited in claim 7 wherein said spectral components X n correspond to the discrete Fourier transformation of a time dependent received signal x(t) and said equalizer comprises means for generating the discrete Fourier transform components X n of said received signal x(t).

Claim 12

A frequency domain equalizer as recited in claim 10 further comprising means for sampling said input signal x(t) for providing a sample set x k , k=0, 1 . . . N-1, where N is an integer, and said means for generating the discrete Fourier transform components X n comprises means for generating N components where n=0, 1 . . . N-1.

Claim 13

A frequency domain equalizer as recited in claim 11 wherein x(t) is real and N is an even integer and n has values in one of the groups consisting of n=0, 1 . . . N/2 and n=0, n/2, (N/2)+1 . . . N-1.

Claim 14

A frequency domain equalizer as recited in claim 12 wherein said equalizer further comprises means for generating the inverse discrete Fourier transform of a plurality of product signals Y n .

Claim 15

A frequency domain equalizer for automatically equalizing the discrete Fourier coefficients X n of a received electrical signal x(t) transmitted through a transmission channel comprising: (a) means for sampling a test pulse transmitted through said transmission channel for providing a discrete set of test sample values f k , where k=0, 1 . . . N-1, and N is an integer; (b) means for calculating the discrete Fourier transform of said test sample values f k to provide the discrete Fourier coefficients F n , n=0, 1 . . . N-1; (c) means for providing reference values H n representing the discrete Fourier coefficients corresponding to an ideal, undistorted test pulse; (d) feedback control means for generating a correction factor C n for each value F n such that C.sub.n.sup. . F.sub. n = H.sub.n, said feedback control means comprising logic circuit means responsive to the algebraic sign of real and imaginary components of said coefficients F n ; (e) means for storing said generated correction factors C n ; (f) means for subsequently sampling said received electrical signal x(t) to provide a discrete set of signal sample values x k , k=0, 1 . . . N-1; (g) means for calculating the discrete Fourier transform of said signal sample values x k to provide the discrete Fourier coefficients X n ; (h) means for multiplying X n by the stored correction factors C n to produce the frequency equalized coefficients Y n for n=0, 1 . . . N-1 where Y.sub. n = C.sub. n.sup.. X.sub.n, and (i) means for generating the inverse discrete Fourier transform of the coefficients Y n to provide an output signal in the time domain corresponding to said received electrical signal.

Claim 16

A frequency domain equalizer for automatically equalizing the discrete Fourier coefficients X n of a received electrical signal x(t) transmitted through a transmission channel comprising: (a) means for sampling a test pulse transmitted through said transmission channel for providing a discrete set of test sample values f k , where k=0, 1 . . . N-1, and N is an integer; (b) means for calculating the discrete Fourier transform of said test sample values f k to provide the discrete Fourier coefficients F n , n=0, 1 . . . N-1; (c) means for providing reference values H n representing the discrete Fourier coefficients corresponding to an ideal, undistorted test pulse; (d) feedback control means for generating a correction factor C n for each value F n such that C.sub.n.sup. . F.sub. n = H.sub.n, said feedback control means comprising logic circuit means responsive to the algebraic sign of real and imaginary components of said coefficients F n ; (e) means for storing said generated correction factors C n ; (f) means for subsequently sampling said received electrical signal x(t) to provide a discrete set of signal sample values x k , k=0, 1 . . . N-1; (g) means for calculating the discrete Fourier transform of said signal sample values x k to provide the discrete Fourier coefficients X n ; (h) means for multiplying X n by the stored correction factors C n to produce the frequency equalized coefficients Y n for n=0, 1 . . . N-1 where Y.sub. n = C.sub. n.sup.. X.sub.n, and (i) means for generating the inverse discrete Fourier transform of the coefficients Y n to provide an output signal in the time domain corresponding to said received electrical signal.

Claim 17

A frequency domain equalizer as recited in claim 14 wherein said feedback control means further comprises: (a) means for comparing the product C.sub. n.sup.. F n with the value H n ; (b) means for generating an error signal having a polarity determined by the algebraic sign of the difference between said compared product C.sub. n.sup.. F n and H n ; and (c) said logic circuit means responsive to the algebraic sign of said error signal.

Claim 18

A frequency domain equalizer as recited in claim 15 wherein said logic circuit means is responsive solely to the algebraic sign of said error signal and the algebraic sign of real and imaginary components of said coefficients F n .

Claim 19

A frequency domain equalizer as recited in claim 16 wherein said received electrical signal x(t) is real, N is an even integer having values in one of the group n=0, 1 . . . N/2 and n=0, N/2, N/2+1 . . . N-1, and said means for generating the inverse discrete Fourier transform comprises means for generating a sparse inverse discrete Fourier transform having only real components of Y n as an input thereof.

Claim 20

A frequency domain equalizer as recited in claim 17 wherein said output signal from said means for generating said sparse inverse discrete Fourier transform comprises a single output value of said discrete signal sample values x k , k=0, 1 . . . N-1.

Claim 21

A frequency domain equalizer as recited in claim 18 wherein said means for sampling said signal x(t) comprises means for providing N samples x k of said signal x(t), each sample spaced a time interval T/N apart, where T is the period of a sample set.

Claim 22

A frequency domain equalizer as recited in claim 19 further comprising an input analog delay line for receiving said signal x(t), said delay line having taps spaced apart at time intervals T/N.

Claim 23

A frequency domain equalizer as recited in claim 19 further comprising means for time shifting said signal x(t) to provide different discrete sets of signal sample values x k , each set time displaced by an amount T/N, whereby a sliding window sampling of said received signal x(t) is provided.

Claim 24

A frequency domain equalizer as recited in claim 14 wherein said means for generating C n comprises means for generating the real, R, and imaginary, I, parts of C n , in terms of the real and imaginary parts of H n and F n as follows: ##EQU6##

Claim 25

A frequency domain equalizer as recited in claim 22 wherein said means for generating C n comprises a time-shared circuit for calculating C n for n=1 . . . N/2- 1, where N is an even integer.

Claim 26

A frequency domain equalizer as recited in claim 14 wherein said means for calculating the discrete Fourier transform of f k and x k , said correction factors C n , and said inverse discrete Fourier transform of Y n comprises analog circuit means.