Threshold logic gates

Claim 2

A threshold logic gate comprising: a plurality of activable input terminals; a counter; scanning means for performing a scanning operation to sequentially scan said input terminals and connected to said counter to add to the count in said counter as each active input terminal is scanned, the scanning operation having a beginning and a conclusion; means responsive to the count in said counter for providing an output signal at the conclusion of the scanning operation indicating whether the count in the counter exceeds a predetermined value; and means for resetting the counter at the beginning of the scanning operation.

Claim 3

A threshold logic gate as claimed in claim 1, wherein said scanning means has a plurality of inputs and including weighting means for applying an integral weighting factor to one of said plurality of input terminals comprising means for connecting said one of said plurality of input terminals to a number of the inputs to said scanning means, said number being equal to the required weighting factor.

Claim 4

A threshold logic gate comprising: a network comprising combinational logic cells arranged in rows and columns and having a plurality of network inputs and a plurality of network outputs; each combinational logic cell having first and second cell inputs, first and second cell outputs, an AND gate and an OR gate, the first and second cell inputs being connected both to respective inputs and the AND gate and to respective inputs of the OR gate, the output of the AND gate forming the first cell output and the output of the OR gate forming the second cell output; the cell at the beginning of each row having its first input connected to a network input and each of the remaining cells of each row having its first input connected to the first output of the next adjacent cell in the row; the cell at the end of each column having its second output connected to a network output and each of the remaining cells in each column having its second output connected to the second input of the next adjacent cell in the column. whereby the signal at each end of the network outputs indicates whether the sum of the signals of the network inputs exceeds a respective predetermined threshold value.

Claim 5

A threshold logic gate comprising: a network comprising combinational logic cells arranged in rows and columns and having a plurality of network inputs and a plurality of network outputs; each combinational logic cell having first and second cell inputs, first and second cell outputs, an AND gate and an OR gate, the first and second cell inputs being connected both to respective inputs and the AND gate and to respective inputs of the OR gate, the output of the AND gate forming the first cell output and the output of the OR gate forming the second cell output; the cell at the beginning of each row having its first input connected to a network input and each of the remaining cells of each row having its first input connected to the first output of the next adjacent cell in the row; the cell at the end of each column having its second output connected to a network output and each of the remaining cells in each column having its second output connected to the second input of the next adjacent cell in the column. whereby the signal at each end of the network outputs indicates whether the sum of the signals of the network inputs exceeds a respective predetermined threshold value.

Claim 6

A threshold logic gate as claimed in claim 3, including a plurality of input terminals; and weighting means for applying an integral weighting factor to one of said plurality of input terminals comprising means for connecting said one of said plurality of input terminals to a number of inputs to said network, said number being equal to the required weighting factor.