Dual in-line package with window frame

Claim 1

An electronic device package having a ceramic base for receiving an integrated circuit chip; a first lead glass layer selectively deposited and fixed on said base; and a lead frame fused in position on said lead glass layer at a selected temperature range; in combination, the improvement comprising means facilitating the encapsulation of an integrated circuit on said base at a second relatively lower temperature range than said selected temperature range by a cover member, said means including: a ceramic window frame substantially coextensive with the top surface of said ceramic base for fusement thereover at substantially the said selected temperature range to present a flat planar surface for maintaining the lead frame fused in position on said base and for providing a protection layer substantially over the entire surface of said lead frame, said window frame having a window centrally formed therein of a size to receive an integrated circuit chip; a second lead glass layer selectively deposited on the underside of said window frame, said second glass layer securing said ceramic window frame to said top surface of said ceramic base sandwiching said lead frame between said window frame and said top surface of said ceramic base; and means for fusing a cover member over said window at said second relatively lower temperature range to protect the electrical integrity of the chip, said means including a gold ring deposited and fixed on the other side of said ceramic window frame circumscribing and contiguous to said window.

Claim 7

The method of manufacturing an integrated circuit package comprising the steps of: forming a ceramic base adapted to receive an integrated circuit chip; selectively depositing a lead glass layer on the top surface of said base; fusing a lead frame in position on the first lead glass layer in a registration permitting electrical interconnection of a chip when mounted therein; forming a ceramic window frame substantially coextensive with the top surface of said base; forming a window centrally located in said frame of a size to receive an integrated circuit chip; selectively depositing a second lead glass layer on the underside of said window frame; placing said window frame coextensively over said lead frame for aligning said window of said window frame to permit the lead frame to electrically receive the integrated circuit chip mounted through said window; fusing together said first and said second lead glass layers at a first selected temperature range, sandwiching the lead frame therebetween; and depositing a gold ring layer around the perimeter of said window on the other side of said window frame permitting the integrated circuit chip to be encased by a cover means adapted to be secured on said gold ring at a second selected temperature range lower than said first selected temperature range for protecting the electrical integrity of the chip.

Claim 8

The method of manufacturing an integrated circuit package comprising the steps of: forming a ceramic base adapted to receive an integrated circuit chip; selectively depositing a lead glass layer on the top surface of said base; fusing a lead frame in position on the first lead glass layer in a registration permitting electrical interconnection of a chip when mounted therein; forming a ceramic window frame substantially coextensive with the top surface of said base; forming a window centrally located in said frame of a size to receive an integrated circuit chip; selectively depositing a second lead glass layer on the underside of said window frame; placing said window frame coextensively over said lead frame for aligning said window of said window frame to permit the lead frame to electrically receive the integrated circuit chip mounted through said window; fusing together said first and said second lead glass layers at a first selected temperature range, sandwiching the lead frame therebetween; and depositing a gold ring layer around the perimeter of said window on the other side of said window frame permitting the integrated circuit chip to be encased by a cover means adapted to be secured on said gold ring at a second selected temperature range lower than said first selected temperature range for protecting the electrical integrity of the chip.