Event monitoring transceiver

Claim 2

Event monitoring apparatus for coupling to and automatically examining at cyclically repeating time intervals the signal conditions on a signal circuit comprising, a. signals receiving monitor means for determining that particular kinds of circuit conditions have occurred on said signal circuit and operative to generate a first data signal upon such occurrences, b. timing means including first means for determining the duration of the occurrence of said particular kinds of signal conditions commencing with the end of a predetermined time period after said monitor means has determined that one of said particular kinds of signal condition has occurred and operative to generate a second data signal denoting the time duration of the aforesaid particular kind of signal condition.

Claim 3

Apparatus as set forth in claim 1 wherein said monitor means simultaneously detects the occurrence of a first type of signal and the absence of a second type of signal, and also includes means for determining that said first type of signal has persisted for a first predetermined time duration.

Claim 4

Apparatus as set forth in claim 1 wherein said signals receiving monitor means is operatively coupled to and receives signals from signal encoding means operative to distinguish between a plurality of signal sequence conditions on the signal circuit and to generate a plurality of output signal sequences which each discretely indicates the occurrence of a particular circuit signal sequence and the duration of the component signals of that sequence.

Claim 5

Apparatus as set forth in claim 1 wherein said timing means includes second means effective to set as desired the duration of said predetermined time period.

Claim 6

Apparatus as set forth in claim 1 wherein said timing means includes second means effective to set said predetermined time period to zero and thereby cause said first means to determine the duration of the occurrence of said particular kind of signal condition commencing immediately after said monitor means has determined that said particular kind of signal condition has occurred.

Claim 7

Apparatus as set forth in claim 1 wherein said monitor means includes means for coupling to and cyclically selectively singly sequentially examining the signal conditions on each of a multiplicity of independent monitored signal circuits.

Claim 8

Apparatus as set forth in claim 1 further including, a. data signals storage means effective to store said first and second data signals from said monitored signal circuit, b. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals for said monitored signal circuit in accordance with the generation of said first and second data signals, c. test-signals-generating signal circuit means monitored by said monitor means and operative to generate a predetermined particular signal condition suitable for processing by said monitor and timing means and storage in said data signals storage means, d. test signals storage means operative to store test signals occurrence and duration signals, and e. comparator means coupled to and receiving test signals and data signals respectively from said test signals storage means and said data signals storage means, said comparator being operative, effective responsive to detection of a difference between said test signals and data signals, to generate an error alarm signal.

Claim 9

Apparatus as set forth in claim 1 further including a. parallel to serial electrical signal input multiplexer means and encoder means, said multiplexer means having an output circuit and a plurality of independent input circuits, each said input circuit being cyclically selectively singly sequentially operatively coupled to said output circuit through said encoder means for a predetermined time interval to thereby deliver to said output circuit a sequence of encoded electrical signals corresponding to the signal condition on each of said input circuits during the time interval that the particular selected input circuit is coupled to the said output circuit, said output circuit being coupled to said monitor means, b. data signals storage means effective to store said first and second data signals from each monitored signal circuit, c. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals for each monitored signal circuit in accordance with the generation of said first and second data signals, d. test-signals-generating means coupled to a plurality of selected ones of said plurality of independent input circuits monitored by said monitor means, and operative to generate a predetermined particular signal condition suitable for processing by said monitor and timing means and storage in said data signals storage means at storage locations corresponding to the input multiplexer input circuit address, e. test signals storage means operative to store test signals occurrence and duration signals, f. first comparator means coupled to and receiving test signals and data signals respectively from said test signals storage means and said data signals storage means, said first comparator being operative when enabled, and effective responsive to detection of a difference between said test signals and data signals, to generate an error alarm signal, and g. test signals input circuits address storage means which stores the input circuit addresses to which said test-signals generating means is coupled, and second comparator means for comparing the instantaneous address of the input circuit then coupled to said monitor means with the addresses stored in said test signals circuits address storage means, said second comparator means generating an enabling signal rendering operative said first comparator means when an address match occurs.

Claim 10

Apparatus as set forth in claim 1 wherein said signals receiving monitor means is operatively coupled to and receives signals from signal encoding means which generate for said signal circuit a discrete pair of binary coded first and second status signals in accordance with the particular circuit conditions then existing, said binary coded circuit status signals having four discrete coded combinations interpretable by said monitor means, said coded combinations being 00, 10, 01, 11.

Claim 11

Apparatus as set forth in claim 2 wherein said signals receiving monitor means is operatively coupled to and receives signals from signal encoding means which generate for said signal circuit a discrete pair of binary coded first and second status signals in accordance with the particular circuit conditions then existing, said binary coded circuit status signals having four discrete coded combinations interpretable by said monitor means, said coded combinations being 00, 10, 01, 11.

Claim 12

Apparatus as set forth in claim 2 wherein said monitor means includes means for remembering the presence and duration of said first type of signal and thereafter detects the occurrence of said second type of signal, and also includes means for determining that said second type of signal has persisted for a second predetermined time duration.

Claim 13

Apparatus as set forth in claim 2 wherein said timing means includes second means effective to set as desired the duration of said predetermined time period.

Claim 14

Apparatus as set forth in claim 2 wherein said timing means includes second means effective to set said predetermined time period to zero and thereby cause said first means to determine the duration of the occurrence of said particular kind of signal condition commencing immediately after said monitor means has determined that said particular kind of signal condition has occurred.

Claim 15

Apparatus as set forth in claim 2 wherein said monitor means includes means for coupling to and cyclically selectively singly sequentially examining the signal conditions on each of a multiplicity of independent monitored signal circuits.

Claim 16

Apparatus as set forth in claim 2 further including, a. data signals storage means effective to store said first and second data signals from said monitored signal circuit, b. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals for said monitored signal circuit in accordance with the generation of said first and second data signals, c. test-signals-generating signal circuit means monitored by said monitor means and operative to generate a predetermined particular signal condition suitable for processing by said monitor and timing means and storage in said data signals storage means, d. test signals storage means operative to store test signals occurrence and duration signals, and e. comparator means coupled to and receiving test signals and data signals respectively from said test signals storage means and said data signals storage means, said comparator being operative, effective responsive to detection of a difference between said test signals and data signals, to generate an error alarm signal.

Claim 17

Apparatus as set forth in claim 2 further including a. parallel to serial electrical signal input multiplexer means and encoder means, said multiplexer means having an output circuit and a plurality of independent input circuits, each said input circuit being cyclically selectively singly sequentially operatively coupled to said output circuit through said encoder means for a predetermined time interval to thereby deliver to said output circuit a sequence of encoded electrical signals corresponding to the signal condition on each of said input circuits during the time interval that the particular selected input circuit is coupled to the said output circuit, said output circuit being coupled to said monitor means, b. data signals storage means effective to store said first and second data signals from each monitored signal circuit, c. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals from each monitored signal circuit in accordance with the generation of said first and second data signals, d. test-signals-generating means coupled to a plurality of selected ones of said plurality of independent input circuits monitored by said monitor means, and operative to generate a predetermined particular signal condition suitable for processing by said monitor and timing means and storage in said data signals storage means at storage locations corresponding to the input multiplexer input circuit address, e. test signals storage means operative to store test signals occurrence and duration signals, f. first comparator means coupled to and receiving test signals and data signals respectively from said test signals storage means and said data signals storage means, said first comparator being operative when enabled, and effective responsive to detection of a difference between said test signals and data signals, to generate an error alarm signal, and g. test signals input circuits address storage means which stores the input circuit addresses to which said test-signals generating means is coupled, and second comparator means for comparing the instantaneous address of the input circuit then coupled to said monitor means with the addresses stored in said test signals circuits address storage means, said second comparator means generating an enabling signal rendering operative said first comparator means when an address match occurs.

Claim 18

Apparatus as set forth in claim 3 wherein said timing means includes a second means effective to set as desired the duration of said predetermined time period.

Claim 19

Apparatus as set forth in claim 3 wherein said timing means includes second means effective to set said predetermined time period to zero and thereby cause said first means to determine the duration of the occurrence of said particular kind of signal condition commencing immediately after said monitor means has determined that said particular kind of signal condition has occurred.

Claim 20

Apparatus as set forth in claim 3 wherein said monitor means includes means for coupling to and cyclically selectively singly sequentially examining the signal conditions on each of a multiplicity of independent monitored signal circuits.

Claim 21

Apparatus as set forth in claim 3 further including, a. data signals storage means effective to store said first and second data signals from said monitored signal circuit, b. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals for said monitored signal circuit in accordance with the generation of said first and second data signals, c. test-signals-generating signal circuit means monitored by said monitor means and operative to generate a predetermined particular signal condition suitable for processing by said monitor and timing means and storage in said data signals storage means, d. test signals storage means operative to store test signals occurrence and duration signals, and e. comparator means coupled to and receiving test signals and data signals respectively from said test signals storage means and said data signals storage means, said comparator being operative, effective responsive to detection of a difference between said test signals and data signals, to generate an error alarm signal.

Claim 22

Apparatus as set forth in claim 3 further including a. parallel to serial electrical signal input multiplexer means and encoder means, said multiplexer means having an output circuit and a plurality of independent input circuits, each said input circuit being cyclically selectively singly squentially operatively coupled to said output circuit through said encoder means for a predetermined time interval to thereby deliver to said output circuit a sequence of encoded electrical signals corresponding to the signal condition on each of said input circuits during the time interval that the particular selected input circuit is coupled to the said output circuit, said output circuit being coupled to said monitor means, b. data signals storage means effective to store said first and second data signals from each monitored signal circuit, c. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals from each monitored signal circuit in accordance with the generation of said first and second data signals, d. test-signals-generating means coupled to a plurality of selected ones of said plurality of independent input circuits monitored by said monitor means, and operative to generate a predetermined particular signal condition suitable for processing by said monitor and timing means and storage in said data signals storage means at storage locations corresponding to the input multiplexer input circuit address, e. test signals storage means operative to store test signals occurrence and duration signals, f. first comparator means coupled to and receiving test signals and data signals respectively from said test signals storage means and said data signals storage means, said first comparator being operative when enabled, and effective responsive to detection of a difference between said test signals and data signals, to generate an error alarm signal, and g. test signals input circuits address storage means which stores the input circuit addresses to which said test-signals generating means is coupled, and second comparator means for comparing the instantaneous address of the input circuit then coupled to said monitor means with the addresses stored in said test signals circuits address storage means, said second comparator means generating an enabling signal rendering operative said first comparator means when an address match occurs.

Claim 23

Apparatus as set forth in claim 3 wherein said signals encoding means generates a discrete pair of binary coded first and second circuit status signals in accordance with the particular circuit conditions then existing, said binary coded circuit status signals having four discrete coded combinations interpretable by said monitor means, said coded combinations being 00, 10, 01, 11.

Claim 24

Apparatus as set forth in claim 3 wherein said signal encoding means includes means for simultaneously detecting the occurrence of a first type of signal and the absence of a second type of signal, and means for determining that said first type of signal has persisted for a first predetermined time duration.

Claim 25

Apparatus as set forth in claim 9 for use in monitoring the signal conditions on telephone circuits, wherein said signal encoding means generates a different one of said coded combinations for each of the telephone circuit conditions of line idle, off-hook, reversed on-hook and reversal.

Claim 26

Apparatus as set forth in claim 9 for use in monitoring the signal conditions on telephone circuits, wherein said signal encoding means generates a different one of said coded combinations for each of the telephone circuit conditions of line idle, off-hook, reversed on-hook and reversal, and wherein said monitor means comprises examining, storing and signal generating means for examining said coded combinations, noting and storing the occurrence and disappearance of specific ones of said combinations, the durations of such combinations, and the sequence in which such combinations occur, and in response to the foregoing, at appropriate times generating control signals and said first and second data signals.

Claim 27

Apparatus as set forth in claim 10 for use in monitoring the signal conditions on telephone circuits, wherein said signal encoding means generates a different one of said coded combinations for each of the telephone circuit conditions of line idle, off-hook, reversed on-hook and reversal.

Claim 28

Apparatus as set forth in claim 10 for use in monitoring the signal conditions on telephone circuits, wherein said signal encoding means generates a different one of said coded combinations for each of the telephone circuit conditions of line idle, off-hook, reversed on-hook and reversal, and wherein said monitor means comprises examining, storing and signal generating means for examining said coded combinations, noting and storing the occurrence and disappearance of specific ones of said combinations, the duration of such combinations, and the sequence in which such combinations occur, and in response to the foregoing, at appropriate times generating control signals and said first and second data signals.

Claim 29

Apparatus as set forth in claim 16 wherein said timing means includes second means effective to set as desired the duration of said predetermined time period.

Claim 30

Apparatus as set forth in claim 21 wherein said timing means includes second means effective to set as desired the duration of said predetermined time period.

Claim 31

Apparatus as set forth in claim 23 wherein said monitor means examining, storing and signal generating means notes and stores the occurrence and disappearance of the off-hook circuit condition, determines whether or not a valid off-hook circuit condition occurred and if so its time duration, and generates and stores first and second data signals corresponding to valid off-hook conditions.

Claim 32

Apparatus as set forth in claim 23 wherein said monitor means examining, storing and signal generating means notes and stores the occurrence and disappearance of the incoming call circuit condition, determines whether or not a valid incoming call circuit condition occurred and if so its time duration, and generates and stores first and second data signals corresponding to valid incoming call conditions.

Claim 33

Apparatus as set forth in claim 23 wherein said monitor means examining, storing and signal generating means notes and stores the occurrence of a valid off-hook condition followed by the occurrence of a valid reversal condition while the off-hook condition is maintained, notes and stores the time duration of such reversal condition, and generates and stores first and second data signals corresponding to a valid originating answered call.

Claim 34

Apparatus as set forth in claim 27 wherein said monitor means examining, storing and signal generating means notes and stores the occurrence and disappearance of the off-hook circuit condition, determines whether or not a valid off-hook circuit condition occurred and if so its time duration, and generates and stores first and second data signals corresponding to valid off-hook conditions.

Claim 35

Apparatus as set forth in claim 27 wherein said monitor means examining, storing and signal generating means notes and stores the occurrence and disappearance of the incoming call circuit condition, determines whether or not a valid incoming call circuit condition occurred and if so its time duration, and generates and stores first and second data signals corresponding to valid incoming call conditions, the occurrence of said incoming call condition being determined by recognition of a signal circuit reversal condition in the absence of a verified off-hook condition.

Claim 36

Apparatus as set forth in claim 27 wherein said monitor means examining, storing and signal generating means notes and stores the occurrence of a valid off-hook condition followed by the occurrence of a valid reversal condition while the off-hook condition is maintained, notes and stores the time duration of such reversal condition, and generates and stores first and second data signals corresponding to a valid originating answered call.

Claim 37

For use in conjunction with event monitoring apparatus of the type for coupling to and automatically examining signal conditions on signal circuits in which such event monitoring apparatus comprises, a. signals receiving monitor means for determining that particular kinds of circuit conditions have occurred on said signal circuits and operative to generate signal circuits data signals delineating such conditions, b. parallel to serial electrical signal input multiplexer means, said multiplexer means having an output circuit and a plurality of independent input circuits, each said input circuit being cyclically selectively singly sequentially operatively coupled to said output circuit for a predetermined time interval to thereby deliver to said output circuit a sequence of electrical signals corresponding to the signal condition on each of said input circuits during the time interval that the particular selected input circuit is coupled to the said output circuit, said output circuit being coupled to said monitor means, c. data signals storage means effective to store said signal circuits data signals from each monitored signal circuit, d. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals from each monitored signal circuit in accordance with the generation of said data signals; The invention of a data processing verifier apparatus comprising, a. test-signals-generating means coupled to a plurality of selected ones of said plurality of independent input circuits monitored by said monitor means, and operative to generate predetermined particular test data signal conditions suitable for processing by said monitor means and storage in said data signals storage means at storage locations corresponding to the input multiplexer input circuit address, b. test signals storage means operative to store test data signals, c. first comparator means coupled to and receiving test data signals and signal circuits data signals respectively from said test signals storage means and said data signals storage means, said first comparator means being operative when enabled, and effective responsive to detection of a difference between said test data signals and signal circuits data signals, to generate an error alarm signal, and d. test data signals input circuits address storage means which stores the input circuit addresses to which said test signals generating means is coupled, and second comparator means for comparing the instantaneous address of the input circuit then coupled to said monitor means with the addresses stored in said test signals circuits address storage means, said second comparator means generating an enabling signal rendering operative said first comparator means when an address match occurs.

Claim 38

For use in conjunction with event monitoring apparatus of the type for coupling to and automatically examining signal conditions on signal circuits in which such event monitoring apparatus comprises, a. signals receiving monitor means for determining that particular kinds of circuit conditions have occurred on said signal circuits and operative to generate signal circuits data signals delineating such conditions, b. parallel to serial electrical signal input multiplexer means, said multiplexer means having an output circuit and a plurality of independent input circuits, each said input circuit being cyclically selectively singly sequentially operatively coupled to said output circuit for a predetermined time interval to thereby deliver to said output circuit a sequence of electrical signals corresponding to the signal condition on each of said input circuits during the time interval that the particular selected input circuit is coupled to the said output circuit, said output circuit being coupled to said monitor means, c. data signals storage means effective to store said signal circuits data signals from each monitored signal circuit, d. event incrementing means coupled to said monitor means and to said data signals storage means effective to increment the stored data signals from each monitored signal circuit in accordance with the generation of said data signals; The invention of a data processing verifier apparatus comprising, a. test-signals-generating means coupled to a plurality of selected ones of said plurality of independent input circuits monitored by said monitor means, and operative to generate predetermined particular test data signal conditions suitable for processing by said monitor means and storage in said data signals storage means at storage locations corresponding to the input multiplexer input circuit address, b. test signals storage means operative to store test data signals, c. first comparator means coupled to and receiving test data signals and signal circuits data signals respectively from said test signals storage means and said data signals storage means, said first comparator means being operative when enabled, and effective responsive to detection of a difference between said test data signals and signal circuits data signals, to generate an error alarm signal, and d. test data signals input circuits address storage means which stores the input circuit addresses to which said test signals generating means is coupled, and second comparator means for comparing the instantaneous address of the input circuit then coupled to said monitor means with the addresses stored in said test signals circuits address storage means, said second comparator means generating an enabling signal rendering operative said first comparator means when an address match occurs.

Claim 39

Apparatus as set forth in claim 36 further including means to read out of said apparatus the data stored in all of said data signals storage means, said test signals storage means and said first comparator means, whereby, said data may be processed to determine the malfunction causing data processing errors by comparing the accuracy or occurrence of errors in the data read out of said data signals storage means for specific ones of said input circuits to which said test signals generating means is coupled.

Claim 40

Apparatus as set forth in claim 36 wherein said test-signals-generating means comprises a call simulator which generates in a programmed sequence a plurality of different kinds of signals corresponding to a plurality of different kinds of signal circuit conditions, different ones of said signals sequence being generated for different time durations.

Claim 41

Data processing verifier apparatus as set forth in claim 36 wherein said event monitoring apparatus with which said verifier is used further includes timing signals generating means which generates groups of a plurality of timing signals each of which groups discretely identifies a different input circuit and corresponding data location in said data signals storage means, selected ones of said timing signals being transmitted to and through said input multiplexer means to data processing verifier control means through which said enabling signal from said verifier second comparator must pass in order to enable said verifier first comparator, said selected ones of said timing signals when not present rendering said control means inoperative to pass said enabling signal.

Claim 42

Data processing verifier apparatus as set forth in claim 36 wherein said event monitoring apparatus with which said verifier is used further includes timing signals generating means which generates groups of a plurality of timing signals each of which groups discretely identifies a different input circuit and corresponding data location in said data signals storage means, selected ones of said timing signals being transmitted to and through said data signals storage means to data processing verifier control means through which said enabling signal from said verifier second comparator must pass in order to enable said verifier first comparator, said selected ones of said timing signals when not present rendering said control means inoperative to pass said enabling signal.

Claim 43

Data processing verifier apparatus as set forth in claim 36 wherein said event monitoring apparatus with which said verifier is used further includes timing signals generating means which generates groups of a plurality of timing signals each of which groups discretely identifies a different input circuit and corresponding data location in said data signals storage means, first selected ones of said timing signals being transmitted to and through said input multiplexer means to data processing verifier control means through which said enabling signal from said verifier second comparator must pass in order to enable said verifier first comparator, and second selected ones of said address signals being transmitted to and through said data signals storage means to said verifier control means, said first and second selected ones of said timing signals when not simultaneously present rendering said control means inoperative to pass said enabling signal.

Claim 44

Apparatus as set forth in claim 36 wherein said data signals storage means of said event monitoring apparatus comprises, accumulating storage means which receives the signal circuits data from said event incrementing means, and passive storage means which from time to time has transferred to it for subsequent read-out upon command the data accumulated in said accumulating storage means, and wherein said data processing verifier test signals storage means comprises accumulating test signals storage means which receives test signals event data from said test signals generating means, and passive test signals storage means which receives and holds from said accumulating test signals storage means for subsequent readout upon command the data accumulated therein whenever said event monitoring apparatus passive storage means has transferred to it the data from its associated accumulating storage means.

Claim 45

Apparatus as set forth in claim 36 wherein said data signals storage means of said event monitoring apparatus comprises, accumulating storage means which receives the signal circuits data from said event incrementing means, and passive storage means which from time to time has transferred to it for subsequent readout upon command the data accumulated in said accumulating storage means, and wherein said data processing verifier test signals storage means comprises accumulating test signals storage means which receives test signals event data from said test signals generating means, and passive test signals storage means which receives and holds from said accumulating test signals storage means for subsequent readout upon command the data accumulated therein whenever said event monitoring apparatus passive storage means has transferred to it the data from its associated accumulating storage means, and means for effecting readout from said passive test signals storage means.

Claim 46

Apparatus as set forth in claim 36 wherein said data processing verifier further includes error alarm signal storage means coupled to and receiving error alarm signals from said comparator means for subsequent readout upon command.

Claim 47

Apparatus as set forth in claim 36 wherein said data processing verifier further includes error alarm signal storage means coupled to and receiving error alarm signals from said comparator means for subsequent readout upon command, and means for effecting readout from said error alarm signal storage means.

Claim 48

Apparatus as set forth in claim 38 wherein said data signals storage means of said event monitoring apparatus comprises, accumulating storage means which receives the signal circuits data from said event incrementing means, and passive storage means which from time to time has transferred to it for subsequent readout upon command the data accumulated in said accumulating storage means, and wherein said data processing verifier test signals storage means comprises accumulating test signals storage means which receives test signals event data from said test signals generating means, and passive test signals storage means which receives and holds from said accumulating test signals storage means for subsequent readout upon command the data accumulated therein whenever said event monitoring apparatus passive storage means has transferred to it the data from its associated accumulating storage means.

Claim 49

Apparatus as set forth in claim 38 wherein said data processing verifier further includes error alarm signal storage means coupled to and receiving error alarm signals from said comparator means for subsequent readout upon command.

Claim 50

Apparatus as set forth in claim 42 wherein said data processing verifier further includes error alarm signal storage means coupled to and receiving error alarm signals from said comparator means for subsequent readout upon command.

Claim 51

Apparatus as set forth in claim 48 further including means for effecting readout from said error alarm signal storage means and from said passive test signals storage means.

Claim 54

The method as set forth in claim 50 including the further step of storing said generated error alarm.

Claim 55

The method as set forth in claim 50 including the further steps of, a. removing from storage said original test data signals and said processed test data signals, b. comparing said processed test data signals with said original test data signals and determining which input circuit addresses produced erroneous processed data, c. determining the equipment malfunction which caused the error by sorting and combining the error containing input circuit addresses.

Claim 56

The method as set forth in claim 51 including the steps of, a. examining for the occurrence of said error alarm signal and upon detection of such occurrence, b. comparing said processed test data signals with said original test data signals and determining which input circuit addresses produced erroneous processed data, c. determining the equipment malfunction which caused the error by sorting and combining the error containing input circuit addresses.

Claim 59

The method as set forth in claim 54 wherein the time duration of said waiting step is selectable as desired.

Claim 60

The method as set forth in claim 54 wherein said step of examining the signal conditions on the signal circuit consists of the steps of, a. examining for the presence of a first type of signal and the absence of a second type of signal, and b. detecting that the presence of the first type of signal has persisted for a first predetermined time duration.

Claim 61

The method as set forth in claim 54 wherein said step of examining the signal conditions on the signal circuit consists of the step of encoding the examined signal condition into a pair of binary coded signals having four discrete interpretable combinations.

Claim 62

The method as set forth in claim 54 wherein said step of examining the signal conditions on the signal circuit consists of the steps of, a. examining the signal conditions on a telephone circuit for the presence of the four discrete circuit conditions of line idle, off-hook, reversal and reversed on-hook, b. encoding the examined signal condition into a pair of binary coded signals having four discrete interpretable combinations, one combination for each of the four aforesaid circuit conditions.

Claim 63

The method as set forth in claim 56 further including the steps of, a. subsequently detecting the presence of said second type of signal and the continued presence of said first type of signal, and b. detecting that the presence of the second type of signal has persisted for a second predetermined time duration.