Phasemeters

Claim 2

A phasemeter for determining the relative angular displacement of two harmonic signal waves derived from transducers, comprising: two trigger devices each for receiving a respective said signal wave and which produce an output pulse each time the respective signal wave passes through a reference level in at least one sense of direction; trigger adjustment means for setting the level at which each said device triggers; a bistable which in operation has first and second stable output states and which receives the output of each said trigger device in such manner that it produces a square wave output the Mark-Space ratio of which is directly related to the relative angular displacement of said two harmonic signal waves; measuring apparatus which receives said bistable square wave output, measures the Mark-Space ratio thereof and produces an output indicative of said relative angular displacement; in which further means are provided for determining each said trigger device set-point comprising, attenuator means for selectively and respectively attenuating said signal waves, and switch means for reversing the inputs to said trigger devices.

Claim 3

A phasemeter as claimed in claim 1 which the measuring apparatus is digital and comprises: a generator of continuous high frequency clock pulses; a first counter; a gate controlled by said bistable output so that said clock pulses are passed to said first counter only when said bistable output assumes a first state; a divider which receives directly said clock pulses and produces an output pulse each time the number of received clock pulses reaches a predetermined number, thus determining a standard countperiod; output means which operate to indicate the total count of said first counter each time said divider produces an output pulse, delay means which receive and delay said divider output pulse which is then directed thereby to rest said first counter and said divider.

Claim 4

A phasemeter according to claim 2 in which means are provided for frequency modulating the output from said generator of clock pulses.

Claim 5

A phasemeter as claimed in claim 3, in which the clock pulse generator comprises a crystal controlled oscillator, a multi-vibrator and a trigger device; the output of the oscillator and the multivibrator being commoned to drive the trigger device to provide a modulated output therefrom.

Claim 6

A phasemeter according to claim 1, in which the measuring apparatus is digital and includes: a clock pulse generator; a logic circuit providing a count-period comprising an integral number of Mark-Space periods; a first counter which counts clock pulses gated to pass only during the mark states of the count period; and a second counter which counts the total number of clock pulses generated during the said count period; the ratio of said counts being a measure of the Mark-Space ratio and of the phase displacement which it represents.

Claim 7

A phasemeter according to claim 5, comprising a calculator which is fed the totals of both said counters, and which divides the count of the first counter by the count of the second counter to provide a measure of said signal wave displacement.

Claim 8

A phasemeter according to claim 6, in which said calculator comprises: one or more data input means; one or more instruction input means; a scanner which periodically scans said data input means; said instruction input means and said first and second counter outputs, in a predetermined sequence; a calculator module which receives the sequence of data and instruction and performs calculation in accordance with said instructions; and output means which present the calculation results.

Claim 9

A phasemeter as claimed in claim 5, wherein said measuring apparatus includes a divider which receives, directly, clock pulses from said clock pulse generator and produces an output pulse at the end of a predetermined count of clock pulses.

Claim 10

A phasemeter according to claim 8, wherein said logic circuit comprises: a flip-flop having a data input and a clock input, an inverter having the input thereof connected to the output of said bistable and the output thereof connected to the clock input of the flip-flop; the data input of the flip-flop being connected to the output of the divider, a first logic gate having an output connected to said first counter, a first input connected to the output of said bistable and a second input connected to the output of said flip-flop, and a second logic gate having an output connected to said second counter, a first input connected to the output of the clock pulse generator and a second input connected to the output of said flip-flop; acting to maintain an enabling signal to both said first and second logic gates to cause them to permit gating of clock pulses to said first and second counters until the divider stops counting and until the end of the mark signal in the mark/space period current when the mark signal in the mark/space period current when the divider stopped counting, whereby the first and second counters are operated to effect their respective counts over an integral number of mark/space periods even though the divider stops counting before the mark/space period then current terminates.

Claim 11

A phasemeter as claimed in claim 8 in which said logic circuit comprises a biased electronic switch, the output of which controls gating of clock pulses to said first and second counters; the switch receiving at its bias input, the output of said bistable, and at a signal input, the output of said divider, so that, for as long as said divider is counting during a count period, the output of the switch permits gating of clock pulses to said first counter in response to mark signals from said bistable and to said second counter throughout each mark space period occurring during the counting of the divider, and so that, when the divider terminates its count, the switch continues to produce the same output until the temination of the mark signal of the mark space period current at the time the divider stopped counting, whereby the phasemeter in each count period operates over an integral number of mark space periods.

Claim 12

A phasemeter according to claim 10, further comprising: a bistable device one input of which is connected to the output of said first logic gate; an inverter the input of which is connected to the output of said clock generator, and the output of which is connected to a second input of said bistable device; and a third logic gate having an input connected to the output of said bistable device, a second input connected to the output of said clock generator and an output connected to the input of said first counter; whereby said third logic gate gates pulses to said first counter during the occurrence of mark signals in each mark/space period.

Claim 13

A torquemeter comprising: an axial, rotatable, torsional member for transmitting rotational power and having two ends; two toothed-wheel members each rigidly attached to a respective end of said torsional member; two transducers in fixed relative angular relationship each associated with a respective toothedwheel member so as to produce a harmonic signal wave when said torsional member rotates, and a phasemeter according to claim 10 to which the transducers connect.

Claim 14

A torquemeter according to claim 2, in which is provided a comparator whereby the amplitudes of said harmonic signal waves are compared thus producing a corrective signal directly related to the difference therebetween; means for receiving the corrective signal and applying a correction to the phasemeter output.

Claim 15

A torquemeter according to claim 25, in which the transducers are electrically excited and said attenuator means of the phasemeter comprise means for reducing the excitation current of either said transducers.

Claim 16

A torquemeter having a rotatable torsional member and including a phasemeter according to claim 14 in which is included a bypass switch whereby said bistable may be bypassed so that said first counter receives un-gated clock pulses and therefore indicates rotational speed of said torsional member.

Claim 17

A phasemeter according to claim 1, in which the measuring apparatus is an integrator of said bistable output.

Claim 18

A phasemeter according to claim 16, in which the integrator comprises: a two-phase generator of clock pulses, having first and second outputs; a gate controlled by said bistable output and to which connects the generator first output so that clock pulses pass through the gate each time the bistable output assumes a first state; an up-down counter, the up input of which receives the gated clock pulses; a digital rate meter through which clock pulses from the generator second output pass to the down input of said up-down counter, and the input of which connects to the output of said up-down counter; display means for displaying the output of said up-down counter.

Claim 19

A phasemeter according to claim 16, in which the integrator comprises: a three phase generator of clock pulses having first, second and third outputs; a gate controlled by said bistable output and to which connects said generator first output so that clock pulses pass through the gate whenever said bistable output assumes a first state; an up-down counter having up and down respective inputs and an output; a first digital ratemeter the input of which is connected to said up-down counter output, and to said second output of the generator; an OR-gate having two inputs and an output, one input of which is connected to said first digital ratemeter output, and the output of which is connected to said first digital ratemeter output, and the output of which is connected to the down input of said up-down counter; one or more second digital ratemeters in series connected between said gate and said up input of said up-down counter; one or more third digital ratemeters in series connected between said generator third and the other OR-gate input; means for applying digitally coded information to the inputs of said second and third digital ratemeters thereby to directly modify the up-down counter output; means for displaying the output of said up-down counter.

Claim 20

A phasemeter as claimed in claim 1, in which said trigger devices are each constituted by a Schmitt trigger device.

Claim 21

A phasemeter as claimed in claim 1 in which said bistable is constituted by a flip-flop.