Solid state digital-to-analog converter

Claim 2

A digital-to-analog converter comprising: a circuit board; first and second identical substrates mounted on said circuit board, each of said substrates comprising a chip of semiconductor material formed with a set of separate IC transistors; a third substrate mounted on said circuit board independently of said first and second substrates, said third substrate having first and second identical sets of resistors deposited thereon with each set comprising a set of connection terminals equal in number to the number of transistors of said first and second substrates, respectively, and having ohmic resistances in accordance with a predetermined pattern; power supply circuit means for supplying electrical power to all of said transistors; conductive means on said circuit board providing interconnection between said transistors and said power supply circuit means, and also between the sets of transistors of said first and second substrates and said first and second sets of connection terminals, respectively, to connect said transistors as individual current sources and to fix the current through each transistor in accordance with a preselected binary weighting pattern, said first and second substrates thereby presenting, in combination with said third substrate, first and second identical sets of individually-activatable current sources; digital input means to receive a digital input and coupled to said transistors to activate said current sources selectively in accordance with the digital input; and analog output means coupled to said transistors to produce an analog output current representing the sum of currents contributed by all of the current sources activated in accordance with the digital input, said analog output means including attenuation means to reduce the magnitude of current contributions from said second set of current sources by a predetermined factor prior to being combined with the current contributions from said first set of current sources.

Claim 3

Apparatus as claimed in claim 1, wherein said attenuation means comprises a current-dividing network including a resistor network formed on said third substrate.

Claim 4

Apparatus as claimed in claim 1, wherein said first and second substrates each consists of exactly four current sources the outputs of which are connected for summation at said analog output means.

Claim 5

A digital-to-analog converter comprising: circuit means comprising means to support IC elements and to effect electrical connections thereto; first and second identical IC elements each formed with an identical set of transistors; first and second identical sets of resistors wherein each set comprises a set of connection terminals equal in number to the number of transistors of said first and second IC elements, respectively, and having ohmic resistances in accordance with a predetermined pattern; power supply means for supplying electrical power to all of said transistors; said circuit means comprising conductive means providing interconnection between all of said transistors and said power supply means, and also between the sets of transistors of said first and second IC elements and said first and second sets of connection terminals, respectively, to connect said transistors as individual current sources and to fix the current through each transistor in accordance with a pre-selected binary weighting pattern, said first and second IC elements presenting, in combination with said first and second sets of resistors, first and second identical sets of individually-activatable current sources such that for any one current source in said first set of current sources there is in said second set of current sources a corresponding identical current source arranged to produce a current having a magnitude identical to that produce by said one current source; digital input means to receive a digital input and coupled to said transistors to activate any of said first and second sets of current sources selectively in accordance with the digital input; and analog output means coupled to said transistors to produce an analog output current representing the sums of currents contributed by all of the current sources activated in accordance with the digital input, said analog output means including attenuation means to reduce the magnitude of current contributions from said second set of transistor current sources by a predetermined factor relative to the current contributions from said first set of transistor current sources.

Claim 6

A digital-to-analog converter comprising: circuit means comprising means to support IC elements and to effect electrical connections thereto; first and second identical IC elements each formed with an identical set of transistors; first and second identical sets of resistors wherein each set comprises a set of connection terminals equal in number to the number of transistors of said first and second IC elements, respectively, and having ohmic resistances in accordance with a predetermined pattern; power supply means for supplying electrical power to all of said transistors; said circuit means comprising conductive means providing interconnection between all of said transistors and said power supply means, and also between the sets of transistors of said first and second IC elements and said first and second sets of connection terminals, respectively, to connect said transistors as individual current sources and to fix the current through each transistor in accordance with a pre-selected binary weighting pattern, said first and second IC elements presenting, in combination with said first and second sets of resistors, first and second identical sets of individually-activatable current sources such that for any one current source in said first set of current sources there is in said second set of current sources a corresponding identical current source arranged to produce a current having a magnitude identical to that produce by said one current source; digital input means to receive a digital input and coupled to said transistors to activate any of said first and second sets of current sources selectively in accordance with the digital input; and analog output means coupled to said transistors to produce an analog output current representing the sums of currents contributed by all of the current sources activated in accordance with the digital input, said analog output means including attenuation means to reduce the magnitude of current contributions from said second set of transistor current sources by a predetermined factor relative to the current contributions from said first set of transistor current sources.

Claim 7

Apparatus as claimed in claim 4, wherein each of said IC elements provides exactly four separate transistors serving as said current sources.

Claim 8

A digital-to-analog converter comprising: integrated circuit means formed with first and second sets of transistors; a first set of resistors with a first set of connection terminals equal in number to the number of transistors of said first set, said first set of resistors having ohmic resistances in accordance with a predetermined pattern; a second set of resistors with a second set of connection terminals equal in number to the number of transistors of said second set, said second set of resistors having ohmic resistances in accordance with a predetermined pattern; power supply means for supplying electrical power to all of said transistors; circuit means comprising conductive means providing interconnections (1) between all of said transistors and said power supply means, (2) between the transistors of said first set of transistors and respective terminals of said first set of resistors, and (3) between the transistors of said second set of transistors and respective terminals of said second set of resistors; said circuit means including means arranged to connect said transistors as individual current sources with said first and second sets of transistors presenting, in combination with said first and second sets of resistors, first and second sets of current sources wherein the currents from each set vary in accordance with a pre-selected binary-weighting pattern and wherein the set of currents produced by said first set of current sources correspond identically in magnitude and weighting pattern to the set of currents produced by said second set of current sources, whereby for any one current source of said first set producing a current of given magnitude there is in said second set of current sources a source producing a current of magnitude equal to said given magnitude; analog output means; and digital input means to receive a digital input, said digital input means being coupled to said transistor current sources to selectively direct the currents thereof to said analog output means in accordance with said digital input; said analog output means including means to produce an analog output current representing a summation of currents from all of said current sources which are selected in accordance with said digital input, said analog output means further including attenuation means to reduce the magnitude of current contributions from said second set of transistor current sources by a predetermined factor relative to the current contributions from said first set of transistor current sources to produce said analog output current.

Claim 9

A digital-to-analog converter comprising: integrated circuit means formed with first and second sets of transistors; a first set of resistors with a first set of connection terminals equal in number to the number of transistors of said first set, said first set of resistors having ohmic resistances in accordance with a predetermined pattern; a second set of resistors with a second set of connection terminals equal in number to the number of transistors of said second set, said second set of resistors having ohmic resistances in accordance with a predetermined pattern; power supply means for supplying electrical power to all of said transistors; circuit means comprising conductive means providing interconnections (1) between all of said transistors and said power supply means, (2) between the transistors of said first set of transistors and respective terminals of said first set of resistors, and (3) between the transistors of said second set of transistors and respective terminals of said second set of resistors; said circuit means including means arranged to connect said transistors as individual current sources with said first and second sets of transistors presenting, in combination with said first and second sets of resistors, first and second sets of current sources wherein the currents from each set vary in accordance with a pre-selected binary-weighting pattern and wherein the set of currents produced by said first set of current sources correspond identically in magnitude and weighting pattern to the set of currents produced by said second set of current sources, whereby for any one current source of said first set producing a current of given magnitude there is in said second set of current sources a source producing a current of magnitude equal to said given magnitude; analog output means; and digital input means to receive a digital input, said digital input means being coupled to said transistor current sources to selectively direct the currents thereof to said analog output means in accordance with said digital input; said analog output means including means to produce an analog output current representing a summation of currents from all of said current sources which are selected in accordance with said digital input, said analog output means further including attenuation means to reduce the magnitude of current contributions from said second set of transistor current sources by a predetermined factor relative to the current contributions from said first set of transistor current sources to produce said analog output current.

Claim 10

Apparatus as claimed in claim 6, wherein said first resistor set comprises a plurality of resistors each connected at one end to the emitter of a corresponding transistor of said first transistor set, and said second resistor set comprises a plurality of resistors each connected at one end to the emitter of a corresponding transistor of said second transistor set; and said power supply means is arranged to apply the same voltage between the base of each of said transistors and the other end of the corresponding resistor connected to the emitter thereof, whereby to provide current sources wherein the current magnitude is controlled by a common applied voltage and by the magnitude of the respective resistor.

Claim 11

A digital-to-analog converter comprising: integrated circuit means formed with first and second sets of transistors; a first set of resistors with a first set of connection terminals equal in number to the number of transistors of said first set, said first set of resistors having ohmic resistances in accordance with a predetermined pattern; a second set of resistors with a second set of connection terminals equal in number to the number of transistors of said second set, said second set of resistors having ohmic resistances in accordance with a predetermined pattern; power supply means for supplying electrical power to all of said transistors; circuit means comprising conductive means providing interconnections (1) between all of said transistors and said power supply means, (2) between the transistors of said first set of transistors and respective terminals of said first set of terminals, (3) between the transistors of said second set of transistors and respective terminals of said second set of terminals; said circuit means including means arranged to connect said transistors as individual current sources with said first and second sets of transistors presenting, in combination with said first and second sets of resistors, first and second sets of current sources wherein the currents from each set vary in accordance with a pre-selected binary weighting pattern and wherein the individual currents produced by said first set of current sources correspond at least approximately in magnitude to the individual currents produced by said second set of current sources such that for any one current source of said first set producing a current of given magnitude there is in said second set of current sources a source producing a current of magnitude at least approximately equal to said given magnitude; the range of current magnitudes of said first set of current sources, from the maximum to minimum thereof, at least substantially overlapping the range of current magnitudes of said second set of current sources, whereby the total overall range of current magnitudes of said first and second sets combined is substantially less than the total range of current magnitudes of a corresponding total number of non-overlapping binarily-weighted current sources; analog output means; and digital input means to receive a digital input, said digital input means being coupled to said transistor current sources to selectively direct the currents thereof to said analog output means in accordance with said digital input; said analog output means including means to produce an analog output current representing a summation of currents from all of said current sources which are selected in accordance with said digital input; said analog output means further including attenuation means to reduce the magnitude of current contribution from said second set of transistor current sources by a predetermined factor relative to the current contributions from said first set of transistor current sources to produce said analog output current, said predetermined factor being set at a value providing that the relatively-reduced current contributions from said second set of current sources are all less in magnitude than the smallest current contribution from said first set of current sources and further providing that said relatively-reduced current contributions relate to said smallest current contribution in accordance with said pre-selected binary weighting pattern so as to produce from said first and second sets of current sources net current contributions having a predetermined successive relationship in accordance with said pre-selected binary weighting pattern to accommodate conversion of said digital input to a corresponding analog output.

Claim 12

A digital-to-analog converter comprising: integrated circuit means formed with first and second sets of transistors; a first set of resistors with a first set of connection terminals equal in number to the number of transistors of said first set, said first set of resistors having ohmic resistances in accordance with a predetermined pattern; a second set of resistors with a second set of connection terminals equal in number to the number of transistors of said second set, said second set of resistors having ohmic resistances in accordance with a predetermined pattern; power supply means for supplying electrical power to all of said transistors; circuit means comprising conductive means providing interconnections (1) between all of said transistors and said power supply means, (2) between the transistors of said first set of transistors and respective terminals of said first set of terminals, (3) between the transistors of said second set of transistors and respective terminals of said second set of terminals; said circuit means including means arranged to connect said transistors as individual current sources with said first and second sets of transistors presenting, in combination with said first and second sets of resistors, first and second sets of current sources wherein the currents from each set vary in accordance with a pre-selected binary weighting pattern and wherein the individual currents produced by said first set of current sources correspond at least approximately in magnitude to the individual currents produced by said second set of current sources such that for any one current source of said first set producing a current of given magnitude there is in said second set of current sources a source producing a current of magnitude at least approximately equal to said given magnitude; the range of current magnitudes of said first set of current sources, from the maximum to minimum thereof, at least substantially overlapping the range of current magnitudes of said second set of current sources, whereby the total overall range of current magnitudes of said first and second sets combined is substantially less than the total range of current magnitudes of a corresponding total number of non-overlapping binarily-weighted current sources; analog output means; and digital input means to receive a digital input, said digital input means being coupled to said transistor current sources to selectively direct the currents thereof to said analog output means in accordance with said digital input; said analog output means including means to produce an analog output current representing a summation of currents from all of said current sources which are selected in accordance with said digital input; said analog output means further including attenuation means to reduce the magnitude of current contribution from said second set of transistor current sources by a predetermined factor relative to the current contributions from said first set of transistor current sources to produce said analog output current, said predetermined factor being set at a value providing that the relatively-reduced current contributions from said second set of current sources are all less in magnitude than the smallest current contribution from said first set of current sources and further providing that said relatively-reduced current contributions relate to said smallest current contribution in accordance with said pre-selected binary weighting pattern so as to produce from said first and second sets of current sources net current contributions having a predetermined successive relationship in accordance with said pre-selected binary weighting pattern to accommodate conversion of said digital input to a corresponding analog output.