US4015288A
Expired / Lapsed
US
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Write clock generator for digital time base corrector
Assignee: Sony Corp
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Filing: 1976-02-13
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Granted: 1977-03-29
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Expires: 1996-02-13
Abstract
Abstract A write clock generator of a digital time base corrector for removing time base errors from color video signals includes a voltage controlled oscillator (VCO) in a phase lock loop by which the oscillator output or write clock pulses, after being suitably divided, are compared, as to phase, with the horizontal synchronizing signals and the burst signals separated from the video signals for controlling the VCO on the basis of both comparisons. In order to avoid a lock-out condition of the phase lock loop as a result of variation in the time relationship of the horizontal synchronizing signals and the onset of the respective burst signals, the oscillator output which has been divided to generally correspond to the frequency of the burst signals is employed to produce first and second trains of pulses having the same frequency as such divided output but being out of phase with respect to each other, and one or the other of the trains of pulses is selected, in response to the timing of the burst signals, for phase comparison with the burst signals of the train of pulses which is substantially out of phase in respect to the latter.
Inventors
- 👤 Norio Ebihara
- 👤 Mitsushige Tatami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:49
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/896
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
273 words
A write clock generator for a digital time base corrector employed for removing time base errors from information signals containing first and second reference signals respectively having different standard frequencies and which may have varying time relations to each other; said write clock generator comprising a voltage controlled oscillator for producing a write clock pulse with a center frequency which is a first multiple of the standard frequency of said first reference signal and a second multiple of the standard frequency of said second reference signal, first and second dividers receiving said write clock pulse and dividing the latter by said first and second multiples, respectively, for providing first and second divided outputs, first and second separators for separating said first and second reference signals, respectively, from the information signals, first phase comparing means receiving the separated first reference signal and said first divided output for producing a first control voltage corresponding to the phase difference therebetween, signal generating means receiving said second divided output and producing at least first and second trains of pulses at the frequency of said second divided output and having different phases from each other, signal selecting means responsive to the separated second reference signal for selecting the one of said trains of pulses which is substantially out of phase in respect to said separated second reference signal, second phase comparing means receiving said separated second reference signal and the selected one of said trains of pulses for producing a second control voltage corresponding to the phase difference therebetween, and means for combining said first and second control voltages so as to control said voltage controlled oscillator therewith.
Claim 2
Dependent Claim
273 words
A write clock generator for a digital time base corrector employed for removing time base errors from information signals containing first and second reference signals respectively having different standard frequencies and which may have varying time relations to each other; said write clock generator comprising a voltage controlled oscillator for producing a write clock pulse with a center frequency which is a first multiple of the standard frequency of said first reference signal and a second multiple of the standard frequency of said second reference signal, first and second dividers receiving said write clock pulse and dividing the latter by said first and second multiples, respectively, for providing first and second divided outputs, first and second separators for separating said first and second reference signals, respectively, from the information signals, first phase comparing means receiving the separated first reference signal and said first divided output for producing a first control voltage corresponding to the phase difference therebetween, signal generating means receiving said second divided output and producing at least first and second trains of pulses at the frequency of said second divided output and having different phases from each other, signal selecting means responsive to the separated second reference signal for selecting the one of said trains of pulses which is substantially out of phase in respect to said separated second reference signal, second phase comparing means receiving said separated second reference signal and the selected one of said trains of pulses for producing a second control voltage corresponding to the phase difference therebetween, and means for combining said first and second control voltages so as to control said voltage controlled oscillator therewith.
Claim 3
Dependent Claim
141 words
A write clock generator according to claim 1; in which said signal selecting means includes a J-K flip-flop having J and K inputs respectively receiving said first and second trains of pulses and a timing input receiving said separated second reference signal, said J-K flip-flop producing a first output when said separated second reference signal and said first train of pulses occur simultaneously and switching over to a second output when said separated second reference signal and said second train of pulses occur simultaneously, first gating means passing said first train of pulses in response to said second output from said J-K flip-flop, second gating means passing said second train of pulses in response to said first output from said J-K flip-flop, and means for connecting the outputs of said first and second gating means to said second phase comparing means.
Claim 4
Dependent Claim
81 words
A write clock generator according to claim 2; in which said signal generating means for producing said first and second trains of pulses includes a monostable-multivibrator receiving said second divided output and producing said first train of pulses in phase therewith, and delay means receiving said first train of pulses and having a delay time substantially equal to one-half the period of said first train of pulses for providing said second train of pulses at the output of said delay means.
Claim 5
Dependent Claim
81 words
A write clock generator according to claim 1; in which said signal generating means for producing said first and second trains of pulses includes a monostable-multivibrator receiving said second divided output and producing said first train of pulses in phase therewith, and delay means receiving said first train of pulses and having a delay time substantially equal to one-half the period of said first train of pulses for providing said second train of pulses at the output of said delay means.
Claim 6
Dependent Claim
122 words
A write clock generator according to claim 1; in which said first phase comparing means includes a first sawtooth generator actuated by said first divided output to produce a corresponding sawtooth signal, and a first phase comparator which detects the level of said sawtooth signal at the occurrence of said separated first reference signal to establish said first control voltage; and in which said second phase comparing means includes a second sawtooth generator actuated by said selected one of the trains of pulses to produce a corresponding sawtooth signal, and a second phase comparator which detects the level of said sawtooth signal from said second sawtooth generator at the occurrence of said separated second reference signal to establish said second control voltage.
Claim 7
Dependent Claim
141 words
A write clock generator according to claim 5; in which said signal selecting means includes a J-K flip-flop having J and K inputs respectively receiving said first and second trains of pulses and a timing input receiving said separated second reference signal, said J-K flip-flop producing a first output when said separated second reference signal and said first train of pulses occur simultaneously and switching over to a second output when said separated second reference signal and said second train of pulses occur simultaneously, first gating means passing said first train of pulses in response to said second output from said J-K flip-flop, second gating means passing said second train of pulses in response to said first output from said J-K flip-flop, and means for connecting the outputs of said first and second gating means to said second phase comparing means.
Claim 8
Dependent Claim
81 words
A write clock generator according to claim 6; in which said signal generating means for producing said first and second trains of pulses includes a monostable-multivibrator receiving said second divided output and producing said first train of pulses in phase therewith, and delay means receiving said first train of pulses and having a delay time substantially equal to one-half the period of said first train of pulses for providing said second train of pulses at the output of said delay means.
Claim 9
Dependent Claim
32 words
A write clock generator according to claim 1; in which said information signals are color video signals including horizontal synchronizing signals and burst signals constituting said first and second reference signals, respectively.
Claim 10
Dependent Claim
42 words
A write clock generator according to claim 1; in which said first and second dividers are respectively first and second counting circuits; and further comprising means operated by the output of said first counting circuit for periodically resetting said second counting circuit.
References Cited (Backward Citations)
US3978519A
Cited
US3974520A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-03-28 | 1980-09-27 | 1981-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-03-28 | 1984-09-27 | 1985-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-03-28 | 1988-09-27 | 1989-03-29 | $7700.00 | Window Closed / Lapsed |