Dual channel pulse width detector having delay and D.C. offset means therein

Claim 2

A pulse width detector comprising: a. an input circuit; b. first and second pulse transmission means coupled to said input circuit, said first transmission means including a delay means therein for delaying pulses emanating from said first channel with respect to pulses emanating from said second channel; c. offsetting means coupled to at least one of said channels for producing a relative shift between the D.C. levels of said pulses emanating from said channels; d. first comparator means coupled to said first and second channels for detecting the voltage crossover points of the leading edges of the pulses emanating from said first and second pulse transmission means; and e. second voltage comparator means coupled to said first and second channels for detecting the voltage crossover points of the trailing edges of the pulses emanating from said first and second pulse transmission means.

Claim 3

The combination as set forth in claim 1 wherein said offsetting means is adjustable to alter the threshold sensitivity of said detector.

Claim 4

The combination as set forth in claim 1 wherein said offsetting means comprises a first biasing means coupled to one channel and a second biasing means coupled to the other channel which produces a different bias of said other channel with respect to said one channel.

Claim 5

The offsetting means as set forth in claim 3 wherein said second biasing means includes a current source.

Claim 6

The combination as set forth in claim 2 further including a digital to analog converter coupled to said offsetting means for precisely and rapidly varying the bias applied by said offsetting means.

Claim 7

The combination as set forth in claim 3 further including a digital to analog converter coupled to at least one of said biasing means for varying the applied bias thereby to precisely and rapidly alter the threshold sensitivity of said detector.

Claim 8

The combination as set forth in claim 4 further including a digital to analog converter coupled to said current source for varying the applied bias thereby to precisely and rapidly alter the threshold sensitivity of said detector.

Claim 9

A pulse width detector comprising: a. an input circuit for receiving pulses having widths to be measured; b. a first and second pulse transmission channel; c. coupling means coupled between said input circuit and said first and second pulse transmission channel for conveying said pulses to said first and second channels wherein the pulses introduced into said first channel are delayed with respect to the pulses introduced into said second channel by a delay means within said coupling means; d. offsetting means for shifting the relative D.C. levels of the pulses emanating from said first and second channels; e. a leading edge pulse comparator coupled to the output circuits of said first and second channels for producing a first signal when the amplitude of the leading edge of the undelayed pulse in said second channel exceeds the amplitude of the delayed pulse in said first channel and for producing a second signal when the amplitude of the leading edge of the delayed pulse in said first channel exceeds the amplitude of the pulse in said second channel; and f. a trailing edge pulse comparator coupled to said first and second channels for producing a third signal when the amplitude of the pulse in said second channel becomes less than the amplitude of the delayed pulse in said first channel and which produces a fourth signal when the amplitude of the delayed pulse in said first channel becomes less than the amplitude of the pulse in said second channel.

Claim 10

A pulse width detector comprising: a. an input circuit for receiving pulses having widths to be measured; b. a first and second pulse transmission channel; c. coupling means coupled between said input circuit and said first and second pulse transmission channel for conveying said pulses to said first and second channels wherein the pulses introduced into said first channel are delayed with respect to the pulses introduced into said second channel by a delay means within said coupling means; d. offsetting means for shifting the relative D.C. levels of the pulses emanating from said first and second channels; e. a leading edge pulse comparator coupled to the output circuits of said first and second channels for producing a first signal when the amplitude of the leading edge of the undelayed pulse in said second channel exceeds the amplitude of the delayed pulse in said first channel and for producing a second signal when the amplitude of the leading edge of the delayed pulse in said first channel exceeds the amplitude of the pulse in said second channel; and f. a trailing edge pulse comparator coupled to said first and second channels for producing a third signal when the amplitude of the pulse in said second channel becomes less than the amplitude of the delayed pulse in said first channel and which produces a fourth signal when the amplitude of the delayed pulse in said first channel becomes less than the amplitude of the pulse in said second channel.

Claim 11

The combination as set forth in claim 8 wherein said offsetting means comprises biasing means coupled to at least one of said channels.

Claim 12

The combination as set forth in claim 9 further including adjustment means for varying the setting of said biasing means to alter the relative degree of offset between the pulses passing through said first and second channel, thereby to alter the pulse amplitude threshold sensitivity of said detector.