Fault bypass for a processor associated scanner

Claim 2

A processor equipment comprising a processor for receiving information from multiplexing means connected to a plurality of peripheral devices, an address counter for controlling said multiplexer means to scan the peripheral devices for processor interrupt signals, a clock generator controlling said address counter, and address lines connecting said address counter to said multiplexing means and said processor enabling the processor to receive the count contained in said counter and to modify said count, the improvement wherein a gate circuit is provided with one clock and two blocking inputs and the clock input of the gate circuit is connected to the clock generator and its output is connected to the address counter, the output of said multiplexing means is connected both with the processor and with the first blocking input of the gate circuit, the processor has a memory unit which stores the address of an interrupting peripheral device from the address counter, and the second blocking input is connected from the processor for inhibiting the gate circuit following an interrupt signal until the next valid address is written into the address counter by the processor.

Claim 3

A processor equipment as claimed in claim 1 wherein the peripheral devices are multiplex units.

Claim 4

A processor equipment as claimed in claim 1 wherein the peripheral devices are telephone handsets.

Claim 5

In a processing system having an input arranged to receive a multiplexed signal from a plurality of peripheral devices, said system including an address counter, a processor having input and output highways connected to the address counter, and a clock means for driving said counter, the method of repeatedly interrogating the peripheral devices for interrupt signals which comprises the steps of: a. applying said multiplexed signal simultaneously to said clock means and said processor respectively to provide a first signal blocking said clock means and to produce a second signal from said processor which blocks said clock means in response to an interrupt signal, whereby said address counter is staticised at that current address corresponding to that peripheral device providing said interrupt signal; b. causing said processor to act upon that peripheral device which produced said interrupt signal whereby, in the absence of a fault, said interrupt signal which provides said first blocking signal is removed; c. storing said current address in said processor in the event that said first blocking signal is not removed in step (b); and d. then writing a new address into said address counter from said processor, which new address is not one previously stored in said processor as in step (c), whereby both said first blocking signal and said second blocking signal are removed to allow further counting by said address counter from said new address.

Claim 6

In a processing system having an input arranged to receive a multiplexed signal from a plurality of peripheral devices, said system including an address counter, a processor having input and output highways connected to the address counter, and a clock means for driving said counter, the method of repeatedly interrogating the peripheral devices for interrupt signals which comprises the steps of: a. applying said multiplexed signal simultaneously to said clock means and said processor respectively to provide a first signal blocking said clock means and to produce a second signal from said processor which blocks said clock means in response to an interrupt signal, whereby said address counter is staticised at that current address corresponding to that peripheral device providing said interrupt signal; b. causing said processor to act upon that peripheral device which produced said interrupt signal whereby, in the absence of a fault, said interrupt signal which provides said first blocking signal is removed; c. storing said current address in said processor in the event that said first blocking signal is not removed in step (b); and d. then writing a new address into said address counter from said processor, which new address is not one previously stored in said processor as in step (c), whereby both said first blocking signal and said second blocking signal are removed to allow further counting by said address counter from said new address.

Claim 7

In the method as defined in claim 4 wherein said peripheral devices are arranged in groups, and wherein the new address written in step (c) is the address in a second group when all peripheral devices belonging to a first group to which said device producing the interrupt signal of step (a) belongs indicate faults as in step (c).