US4005478A
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Process and arrangement for representing digital data by binary signals
Assignee: Wincor Nixdorf International GmbH
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Filing: 1975-07-23
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Granted: 1977-01-25
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Expires: 1995-07-23
Abstract
Abstract In a process for representing digital data by binary signals, in which the data are in the form of binary-coded, ternary-coded characters, or characters coded in a higher value code, the characters are fed in the form of data signals to a data transmitter which assigns binary signals to the characters. The binary signals are transmitted over a transmission channel to a data receiver which regains the digital data from the binary signals. The possible combinations of a given number of characters which form a group of characters are each assigned at least one combination of a plurality of signal elements, each of which represents a binary signal and forms a group of signal elements. The combination, in each case, contains first signal elements representing a first or a second amplitude value and/or second signal elements representing a change in the amplitude value. The assignment is carried out in such a manner that within each group of signal elements and with any arbitrary sequence of the groups of signal elements, always at least one plurality of first signal elements occurs between two second signal elements. The characters which are fed to the data transmitter are divided into groups of the given number, and the groups of characters are represented, in accordance with the assignment, by the groups of signal elements.
Inventors
- 👤 Manfred Beinhauer
- 👤 Eckhart Scharkowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:07
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
199 words
A process for representing digital data by binary signals, in which the data are in the form of binary, ternary or higher value coded characters, in which the characters are fed in the form of data signals to a transmitter which assigns binary signals to the characters, and in which the binary signals are transmitted over a transmission channel to a data receiver which regains the digital data from the binary signals, comprising the steps of: assigning at least one combination of signal elements to each of the possible combinations of a given number of characters which form a group of characters; each signal element combination formed by assigning first signal elements to represent a first or a second amplitude value and assigning second signal elements to represent a change in the amplitude value; the last-mentioned assignments of signal elements including the step of providing, in each arbitrary sequence of the groups of signal elements, at least a plurality of the first signal elements between two second signal elements; dividing the characters fed to the transmitter into groups of the given number; and representing the groups of characters, in accordance with the assignment by the groups of signal elements.
Claim 2
Dependent Claim
199 words
A process for representing digital data by binary signals, in which the data are in the form of binary, ternary or higher value coded characters, in which the characters are fed in the form of data signals to a transmitter which assigns binary signals to the characters, and in which the binary signals are transmitted over a transmission channel to a data receiver which regains the digital data from the binary signals, comprising the steps of: assigning at least one combination of signal elements to each of the possible combinations of a given number of characters which form a group of characters; each signal element combination formed by assigning first signal elements to represent a first or a second amplitude value and assigning second signal elements to represent a change in the amplitude value; the last-mentioned assignments of signal elements including the step of providing, in each arbitrary sequence of the groups of signal elements, at least a plurality of the first signal elements between two second signal elements; dividing the characters fed to the transmitter into groups of the given number; and representing the groups of characters, in accordance with the assignment by the groups of signal elements.
Claim 3
Dependent Claim
37 words
The process of claim 1, wherein the step of providing first signal elements between second signal elements is further defined as providing no more than a predetermined number of first signal elements between two second signal elements.
Claim 4
Dependent Claim
35 words
The process of claim 1, wherein the step of assigning of signal elements to a group of characters is defined as assigning signal elements to a group of characters independently of adjacent groups of characters.
Claim 5
Dependent Claim
31 words
The process of claim 1, wherein the step of assigning signal elements to a group of characters is defined as assigning the signal elements in dependence on adjacent groups of characters.
Claim 6
Dependent Claim
26 words
The process of claim 4, wherein the step of assigning is further defined as assigning the signal elements in dependence upon the preceding group of characters.
Claim 7
Dependent Claim
37 words
The process of claim 1, in which the transmission channel includes a store, and comprising the step of supplying the transmission channel with binary signals having amplitude values corresponding to the code states of the storage medium.
Claim 8
Dependent Claim
28 words
The process of claim 6, in which the store is a magnetic store having saturation magnetizations, and comprising the step of assigning the amplitude values to the magnetizations.
Claim 9
Dependent Claim
173 words
A circuit arrangement for representing data by binary signals in which the data are in the form of binary, -ternary-or higher-coded characters, comprising: a transmission channel; a transmitter for receiving the characters and assigning binary signals to the characters, said transmitter connected to said transmission channel to input the binary signals thereto; said transmitter including a converter which receives the data signals and which comprises a first register for receiving a first group of characters, a coder matrix connected to the outputs of said first register to assign a group of binary signal elements to a group of characters, a second register which is a shift register connected to said coder matrix for receiving the binary encoded values assigned to a group of signal elements in parallel form, and a flip-flop connected to the output of said shift register to receive and output the binary values in serial form to said transmission channel; and a data receiver connected to said transmission channel for receiving, and regaining the data signals from, the binary signals.
Claim 10
Dependent Claim
173 words
A circuit arrangement for representing data by binary signals in which the data are in the form of binary, -ternary-or higher-coded characters, comprising: a transmission channel; a transmitter for receiving the characters and assigning binary signals to the characters, said transmitter connected to said transmission channel to input the binary signals thereto; said transmitter including a converter which receives the data signals and which comprises a first register for receiving a first group of characters, a coder matrix connected to the outputs of said first register to assign a group of binary signal elements to a group of characters, a second register which is a shift register connected to said coder matrix for receiving the binary encoded values assigned to a group of signal elements in parallel form, and a flip-flop connected to the output of said shift register to receive and output the binary values in serial form to said transmission channel; and a data receiver connected to said transmission channel for receiving, and regaining the data signals from, the binary signals.
Claim 11
Dependent Claim
35 words
The circuit arrangement of claim 8, wherein said first register is a shift register which is connected to receive the data signals in series and output the data signals to said coder matrix in parallel.
Claim 12
Dependent Claim
67 words
The circuit arrangement of claim 8, comprising: a third register connected to receive a preceding set of data signals in series from said first register; and a switching stage connected between the outputs of said first and third registers and said coder matrix and operable to control the assignment of signal elements by said coder matrix in accordance with the contents of said first and third registers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-25 | 1980-07-26 | 1981-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-25 | 1984-07-26 | 1985-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-25 | 1988-07-26 | 1989-01-25 | $7700.00 | Window Closed / Lapsed |