Phase equalized readback apparatus and methods

Claim 3

The method set forth in claim 1 further including the steps of: summing said deviations between said reference signal and said readback signal for a predetermined characteristic of said readback signal; storing said summation; repeating said summation; and comparing two of said summations for determining the phase adjustment of said readback signal in accordance with said indication.

Claim 4

The method set forth in claim 2 further including the steps of: comparing said reference signal and said readback signal each transition of said readback signal; counting said comparisons which yield a deviation; and phase adjusting said readback signal in accordance with said indication after a predetermined number of said comparisons.

Claim 5

The method set forth in claim 3 establishing a sign of phase adjustment direction for each said summation; for the sign of each phase adjustment, comparing the signs of two successive ones of said summations and, if the signs are equal, reversing the direction of phase adjustment.

Claim 6

The method set forth in claim 4 further including the step of generating a phase adjustment size independent of said summation.

Claim 7

The method set forth in claim 1 further including the step of counting said comparisons yielding said indicated deviations; and phase adjusting after a predetermined number of said deviation-causing comparisions independent of the size of said deviations.

Claim 10

The method set forth in claim 7 wherein the step of adaptively equalizing includes the step of indicating errors in said readback signals; counting the number of errors; summing the error and its direction; memorizing the sum and direction of the error; and repeating the above steps and comparing the summations and the sign and adaptively equalizing in accordance with said comparison.

Claim 11

For a readback circuit of a magnetic recorder, a readback signal peak shifting circuit comprising: a controllable peak shifter circuit for receiving a periodic signal to have peak shift adjustments; a phase-locked loop (PLL) circuit receiving the peak adjusted signal from said peak shifting circuit and generating a phase error signal, circuit means digitizing the phase error signal in accordance with its time duration; integration circuit means receiving said digitized signals and holding integrating signals generated from same for comparison with other integrated signals generated from later received digitized signals; compare circuit means comparing the integrated signals at predetermined times; timing circuit means responsive to said PLL to time all said circuits and circuit means; timed circuit means responsive to said comparing circuit means to supply an adjustment signal; and an up/down counter circuit for adjusting its count in accordance with said adjustment signal for variably controlling said peak shifter in accordance with an accumulation of said adjustment signals.

Claim 12

For a readback circuit of a magnetic recorder, a readback signal peak shifting circuit comprising: a controllable peak shifter circuit for receiving a periodic signal to have peak shift adjustments; a phase-locked loop (PLL) circuit receiving the peak adjusted signal from said peak shifting circuit and generating a phase error signal, circuit means digitizing the phase error signal in accordance with its time duration; integration circuit means receiving said digitized signals and holding integrating signals generated from same for comparison with other integrated signals generated from later received digitized signals; compare circuit means comparing the integrated signals at predetermined times; timing circuit means responsive to said PLL to time all said circuits and circuit means; timed circuit means responsive to said comparing circuit means to supply an adjustment signal; and an up/down counter circuit for adjusting its count in accordance with said adjustment signal for variably controlling said peak shifter in accordance with an accumulation of said adjustment signals.

Claim 13

The readback signal peak shifting circuit set forth in claim 9 and further including: sign means determining direction of said up/down counter circuit adjustment; means; memorizing direction of said adjustment; and comparison means responsive to said memorized sign and another of said signs to change direction of said adjustment when the signs are equal.

Claim 14

The apparatus set forth in claim 10 wherein said integration circuit means includes first and second integrators; sequencing circuit means responsive to said digitized phase error circuit means to alternately actuate said integrators to integrate the digitized phase error signals; and threshold means responsive to said digitizing circuit means to actuate said sequencer for alternating said integration and simultaneously actuating said compare circuit means for comparihng the integrator results.

Claim 15

The apparatus set forth in claim 10 further including error counter circuit means responsive to said phase-locked loop circuit for indicating the number of successive phase error signals; and threshold means responsive to said error counter to actuate said timing circuit means and said timed circuit means for initiating a phase adjustment.

Claim 16

The apparatus set forth in claim 10 wherein said timed circuit means actuates said up/down counter means by a unitary adjustment signal each time a phase adjustment is called for.