US4002962A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase locked servo loop circuit
Assignee: United States Department of the Navy
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Filing: 1973-10-01
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Granted: 1977-01-11
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Expires: 1993-10-01
Abstract
Abstract Described herein is a phase locked servo loop circuit which causes a DC mr to operate synchronously regardless of DC motor load. The circuit comprises a pick-off device which generates an integral number of voltage pulses each time the motor rotates through 360° and a clock pulse generator that provides fixed frequency pulses. The output pulse of the pick-off device is applied to the input of a logic circuit which either opens or closes a switch in response to phase differences between the train of pick off pulses and the train of clock pulses to control the speed of the motor.
Inventors
- 👤 Samuel A. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:08
CPC Classifications
H; H02; H02P; H02P23/00; H02P23/22; Y; Y10; Y10S; Y10S388/00; Y10S388/907; Y10S388/911
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
386 words
A phase locked servo control system loop for changing the speed of a direct current motor operating under varying load conditions to maintain a constant predetermined motor speed comprising: reference pulse means for providing a first control signal of a series of successive pulses having a substantially fixed repetition rate in accordance with a predetermined desired operation of said motor; speed responsive means operatively connected to sense the speed of said motor for providing a second control signal output of successive electrical pulses having a repetition rate proportional to actual rotation of said motor; pulse responsive means electrically coupled to receive successive pulses from said reference pulse means and said speed responsive means for providing a train of output pulses of varying pulse width having a pulse width time duration dependent on the phase difference between individual successive pulses of first control signals generated by said reference pulse means and individual successive pulses of second control signals generated by said speed responsive source; detector means operatively coupled to said pulse responsive means and to gating control means for supplying a pulsed output control signal whenever the time interval between each second control signal pulse is less than the time interval between each first control signal pulse; coincidence means having inputs electrically coupled to receive output signals from said pulse responsive means and said detector means for producing an output in response to identical output signals; overspeed responsive means coupled to receive signals from said coincidence means and said speed responsive means for supplying output pulse signals in response to said motor overspeed; control logic circuit means coupled to accept output pulse signals from said overspeed responsive means for preventing said reference pulse means first control signals from being received by said pulse responsive means; and switching means operatively connected to receive an electrical output from said pulse responsive means for supplying current to said motor in response to the time duration of the pulses for maintaining the rotation of the motor at its predetermined desired operation. thereby causing the switching means from supplying current to the motor until such time as the motor speed decreases to cause said second control signal pulse to occur at the same time as said first control signal pulse at which time the predetermined desired operation of said motor is reached.
Claim 2
Dependent Claim
386 words
A phase locked servo control system loop for changing the speed of a direct current motor operating under varying load conditions to maintain a constant predetermined motor speed comprising: reference pulse means for providing a first control signal of a series of successive pulses having a substantially fixed repetition rate in accordance with a predetermined desired operation of said motor; speed responsive means operatively connected to sense the speed of said motor for providing a second control signal output of successive electrical pulses having a repetition rate proportional to actual rotation of said motor; pulse responsive means electrically coupled to receive successive pulses from said reference pulse means and said speed responsive means for providing a train of output pulses of varying pulse width having a pulse width time duration dependent on the phase difference between individual successive pulses of first control signals generated by said reference pulse means and individual successive pulses of second control signals generated by said speed responsive source; detector means operatively coupled to said pulse responsive means and to gating control means for supplying a pulsed output control signal whenever the time interval between each second control signal pulse is less than the time interval between each first control signal pulse; coincidence means having inputs electrically coupled to receive output signals from said pulse responsive means and said detector means for producing an output in response to identical output signals; overspeed responsive means coupled to receive signals from said coincidence means and said speed responsive means for supplying output pulse signals in response to said motor overspeed; control logic circuit means coupled to accept output pulse signals from said overspeed responsive means for preventing said reference pulse means first control signals from being received by said pulse responsive means; and switching means operatively connected to receive an electrical output from said pulse responsive means for supplying current to said motor in response to the time duration of the pulses for maintaining the rotation of the motor at its predetermined desired operation. thereby causing the switching means from supplying current to the motor until such time as the motor speed decreases to cause said second control signal pulse to occur at the same time as said first control signal pulse at which time the predetermined desired operation of said motor is reached.
Claim 3
Dependent Claim
169 words
The phase locked servo control system of claim 6 in addition comprising; said detector means being operatively coupled to said pulse responsive means for generating control signal output whenever the time interval between each second control signal pulse is greater than the time interval between each first control signal pulse; and first and second coincidence gate means responsive to outputs from said detector means and said pulse responsive means for providing an inhibit control signal from said first coincidence gate means to stop first control signals from outputting from said reference pulse means and a energizing control signal from said second coincidence gate means for said switch control means to supply current for increasing the speed of said motor to cause said second control signal pulse to occur at the same time as said first control signal pulse at which the predetermined desired operation of said motor is reached; thus, providing motor speed to lock on only the frequency of the reference pulse means first control signal repetition rate.
Claim 4
Dependent Claim
90 words
The phase locked servo control system of claim 1 wherein said pulse responsive means comprises: a control bistable multivibrator circuit having a first input operatively connected to said reference pulse means and second input means operatively connected to said speed responsive means for generating a first and second complementary pulse outputs, each pulse output starting on the positive leading edge of each pulse of first control signal received by said first input and ending on said second input receiving the positive leading edge of each pulse of second control signal.
Claim 5
Dependent Claim
23 words
The phase locked servo control system of claim 1 wherein said synchronous detector comprises: a bistable multivibrator having first and second complementary outputs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |