Single amplifier immittance network

Claim 2

An immittance network comprising: an input terminal and a common terminal; an operational amplifier having an inverting input, a non-inverting input and an output; first and second admittances (Y 1 , Y 2 ) connected in series between said inverting and non-inverting inputs respectively; a third admittance (Y 3 ) connected between said inverting input and said output; fourth and fifth admittances (Y 4 , Y 5 ) connected in series between said non-inverting input and said output respectively; a sixth admittance (Y 6 ) connected between said common terminal and the junction of said fourth and fifth admittances (Y 4 , Y 5 ); a seventh admittance (Y 7 ) connected between said junction and said inverting input; and an eighth admittance (Y 8 ) connected between the junction of the first and second admittances and the input terminal; the values of said admittances having the relationship: ##EQU7## where: Z = the input impedance of the network across said terminals.

Claim 3

An immittance network as defined in claim 1 which simulates a series resonant L-C-R network in which: the admittance Y 1 is a resistor R 1 ; the admittance Y 2 is a resistor R 2 ; the admittance Y 3 is a resistor R 3 ; the admittance Y 4 is a series connected resistor R 4 and a capacitor C 4 ; the admittance Y 5 is a resistor R 5 ; the admittance Y 6 is a resistor R 6 ; the admittance Y 7 is a capacitor C 7 ; and the admittance Y 8 is a resistor R 8 ; the values of the resistors and capacitors having the relationship: ##EQU8## where: C = the input capacitance of the network; L = the input inductance of the network; and R = the input resistance of the network.

Claim 4

An immittance network as defined in claim 2 in which the absolute value of the resistor R 8 equals the negative resistance of the balance of the network, whereby the input resistance R = 0.

Claim 5

An immittance network as defined in claim 2 having a unidirectional tuning sequence in which the resistor R 1 is first adjusted to obtain the input capacitance C, the resistor R 4 is then adjusted to obtain the input inductance L, and finally the resistor R 8 is adjusted to obtain the input resistance R.

Claim 6

An immittance network as defined in claim 1 which simulates a series connected R-D-C network in which: the admittance Y 1 is a resistor R 1 ; the admittance Y 2 is a resistor R 2 ; the admittance Y 3 is a resistor R 3 ; the admittance Y 4 is a capacitor C 4 ; the admittance Y 5 is a resistor R 5 ; the admittance Y 6 is a capacitor C 6 ; the admittance Y 7 is an open circuit; and the admittance Y 8 is a resistor R 8 ; the values of the resistors and capacitors having the relationship: ##EQU9## where: R = the input resistance of the network; D = the input frequency dependent negative resistance of the network; and C = the input capacitance of the network.

Claim 7

An immittance network as defined in claim 5 in which the input capacitance C of the network is essentially infinity.

Claim 8

An immittance network as defined in claim 5 having a unidirectional tuning sequence in which the resistor R 1 is first adjusted to obtain the input resistance R, the resistor R 5 is then adjusted to obtain the frequency dependent negative resistance D, and finally the resistor R 3 is adjusted to obtain the input capacitance C.

Claim 9

An immittance network which simulates a series connected R-D-C network, comprising: an input terminal and a common terminal; an operational amplifier having an inverting input, a non-inverting input and an output; first and second admittances (Y 1 , Y 2 ) connected in series between said inverting and non-inverting inputs respectively, means for connecting the junction of said admittances to said input terminal; a third admittance (Y 3 ) connected between said inverting input and said output; fourth and fifth admittances (Y 4 , Y 5 ) connected in series between said non-inverting input and said output respectively; a sixth admittance (Y 6 ) connected between said common terminal and the junction of said fourth and fifth admittances (Y 4 , Y 5 ); the values of said admittances having the relationship: ##EQU10## where: Z = the input impedance of the network across said terminals; the admittance Y 1 being a resistor R 1 ; the admittance Y 2 being a resistor R 2 ; the admittance Y 3 being a resistor R 3 ; the admittance Y 4 being a capacitor C 4 ; the admittance Y 5 being a resistor R 5 ; the admittance Y 6 being a capacitor C 6 ; the values of the resistors and capacitors having the relationship: ##EQU11## where: R = the input resistance of the network; D = the input frequency dependent negative resistance of the network; and C = the input capacitance of the network.

Claim 10

An immittance network which simulates a series connected R-D-C network, comprising: an input terminal and a common terminal; an operational amplifier having an inverting input, a non-inverting input and an output; first and second admittances (Y 1 , Y 2 ) connected in series between said inverting and non-inverting inputs respectively, means for connecting the junction of said admittances to said input terminal; a third admittance (Y 3 ) connected between said inverting input and said output; fourth and fifth admittances (Y 4 , Y 5 ) connected in series between said non-inverting input and said output respectively; a sixth admittance (Y 6 ) connected between said common terminal and the junction of said fourth and fifth admittances (Y 4 , Y 5 ); the values of said admittances having the relationship: ##EQU10## where: Z = the input impedance of the network across said terminals; the admittance Y 1 being a resistor R 1 ; the admittance Y 2 being a resistor R 2 ; the admittance Y 3 being a resistor R 3 ; the admittance Y 4 being a capacitor C 4 ; the admittance Y 5 being a resistor R 5 ; the admittance Y 6 being a capacitor C 6 ; the values of the resistors and capacitors having the relationship: ##EQU11## where: R = the input resistance of the network; D = the input frequency dependent negative resistance of the network; and C = the input capacitance of the network.