Mode control computer interface

Claim 2

In a computer network wherein plural computers must be simultaneously activated and deactivated, the improvement of a mode control interface for providing simultaneous operation of said computers, and comprising: a plurality of control circuits coupled between a first of said computers and other of said computers, each of said control circuits being responsive to a voltage input to provide an isolated voltage output pulse of predetermined time duration; a control switch coupled to said control circuits for providing activating power to said interface; a first of said control circuits being an AND gate having first and second inputs, first and second series connected inverters coupled between the said first computer and said first input of said AND gate, a transistor switch coupled to the output of said AND gate, a relay coupled in series with said transistor and the activating power from said control switch, and a control of said relay coupled to other of said computers for coupling power therethrough when activated by said relay; and a monostable multivibrator having an output connected to the second input of said AND gate for providing a predetermined signal pulse width thereto and having the input thereof coupled between said series connected inverters for receiving an activating pulse therefrom.

Claim 3

A mode control interface as set forth in claim 1 wherein a second of said control circuits comprises a second AND gate having first and second inputs, a NAND gate and a third inverter being series connected between the first input of said second AND gate and the first computer, the output of said inverter being coupled to said AND gate input, a first input of said NAND gate being coupled to said first computer and a second input of said NAND gate being coupled to said series connection between the first and second inverters, a second transistor switch coupled to the output of said second AND gate, a second relay coupled in series with said second transistor across said control switch activating power source, and a contact of said second relay for coupling to other of said computers for providing power therethrough when activated by said relay; the junction between said NAND gate and said third inverter being coupled to provide an input pulse to said multivibrator; and the output of said multivibrator being connected to a second input of said second AND gate.

Claim 4

A mode control interface as set forth in claim 2 wherein a third of said control circuits comprises a third AND gate; a gating circuit having an input coupled to said first computer and an output coupled to a first input of said third AND gate, a third transistor switch coupled to the output of said thrid AND gate, a third relay coupled in series with said third transistor across the power source from said control switch, and a contact of said third relay for coupling to other of said computers for providing power therethrough when activated by said relay, and a pulse network coupled between the input of said gating circuit and the input of said multivibrator for providing a gating pulse thereto; and the output of said multivibrator being coupled as a second input to said third AND gate.

Claim 5

A mode control interface as set forth in claim 3 wherein a fourth of said control circuits comprises a second input of said gating circuit resistively coupled to said first computer for activation thereby and a pulse network coupled between the second input of said gating circuit and the input of said multivibrator.

Claim 6

A mode control interface as set forth in claim 4 and further comprising a fourth AND gate having first and second inputs and an output, a fourth transistor switch coupled to the output of said fourth AND gate, a forth relay coupled in series with said fourth transistor across the power source from said control switch, and a contact of said fourth relay disposed for coupling to other of said computers for providing power therethrough when activated by said relay; a second NAND gate having first and second inputs and an output, a fourth inverter coupled between the output of said gating circuit and a first input of said second NAND gate, a fifth inverter coupled between the output of said second NAND gate and the first input of said fourth AND gate, a third NAND gate having a first input coupled to the output of the first NAND gate and having a second input coupled to the second input of the first NAND gate, a sixth inverter coupled between the output of said third NAND gate and the second input of said third NAND gate and the second input of said second NAND gate for selectively activating said second NAND gate and said fourth AND gate only during preselected conditions of said plural control circuits; the output of said second NAND gate being further coupled to provide an input pulse to said multivibrator; and the output of said multivibrator being coupled as a second input to said fourth AND gate.