US4000401A
Expired / Lapsed
US
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Hybrid multivariate analog function generator
Assignee: Hughes Missile Systems Co
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Filing: 1975-10-20
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Granted: 1976-12-28
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Expires: 1995-10-20
Abstract
Abstract Apparatus for generating an analog output F(x,y) according to the relationship F ij (x,y) = K 1 (a ij + b ij x) + K 2 ((c ij + d ij x) y). The coefficients and the x and y values are supplied to the appartus by a digital computer. Interpolation circuitry compares sample x and y values to select the address in the x and y arrays corresponding to the x and y sample values. An analog part of the apparatus is fed the sample x and y values and the corresponding coefficients and produces the function F(x,y).
Inventors
- 👤 Neil R. Quinn, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:04
CPC Classifications
G; G06; G06J; G06J1/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
465 words
Apparatus for generating an analog output signal in accordance with a desired function of at least two independent variables, comprising: memory means for storing arrays of a first independent variable, a second independent variable, and first, second, third and fourth coefficients corresponding to combinations of said first and second independent variables at predetermined intervals; input means for placing sample first and second independent variable signals into the apparatus; processing means for comparing said sample first and second independent variable signals with said stored first and second independent variable arrays to select addresses in said stored arrays of coefficients corresponding to combinations of said sample independent variable signals; and function generator means responsive to the processing means for combining digital signals representing said coefficients at said selected addresses with said sample independent variable signals to produce a continuous analog output signal, said function generator means comprising first digital to analog converter means for converting said first coefficient signal into a first analog signal, first multiplying digital to analog converter means for multiplying said second coefficient signal times said sample first variable signal to produce a second analog signal, first summer means for producing a third analog signal representing the sum of said first and second analog signals, second digital to analog converter means for converting said third coefficient signal into a fourth analog signal, second multiplying digital to analog converter means for multiplying said fourth coefficient signal times said sample first variable signal to produce a fifth analog signal, second summer means for producing a sixth analog signal representing the sum of said fourth and fifth analog signals, analog multiplier means for multiplying said sixth analog signal by said sample second variable signal to produce a seventh analog signal, and third summer means for producing a said continuous analog output signal representing the sum of said third and seventh analog signals, thereby providing said desired function at said selected addresses corresponding to said sample first and second independent variable signals; and wherein said processing means comprises: first buffer storage means for storing said sample first variable signal, second buffer storage means for storing said sample second variable signal, first interpolation means for comparing said sample first variable signal in the first buffer storage means with said stored first independent variable array to determine the address in said stored first independent variable array corresponding to said sample first variable signal, second interpolation means for comparing said sample second variable signal in the second buffer storage means with said stored second independent variable array to determine the address in said stored second independent variable array corresponding to said sample second variable, and coefficient addressor means for combining said determined addresses corresponding to said sample first and second independent variable signals to select the addresses of said corresponding coefficients.
Claim 2
Dependent Claim
465 words
Apparatus for generating an analog output signal in accordance with a desired function of at least two independent variables, comprising: memory means for storing arrays of a first independent variable, a second independent variable, and first, second, third and fourth coefficients corresponding to combinations of said first and second independent variables at predetermined intervals; input means for placing sample first and second independent variable signals into the apparatus; processing means for comparing said sample first and second independent variable signals with said stored first and second independent variable arrays to select addresses in said stored arrays of coefficients corresponding to combinations of said sample independent variable signals; and function generator means responsive to the processing means for combining digital signals representing said coefficients at said selected addresses with said sample independent variable signals to produce a continuous analog output signal, said function generator means comprising first digital to analog converter means for converting said first coefficient signal into a first analog signal, first multiplying digital to analog converter means for multiplying said second coefficient signal times said sample first variable signal to produce a second analog signal, first summer means for producing a third analog signal representing the sum of said first and second analog signals, second digital to analog converter means for converting said third coefficient signal into a fourth analog signal, second multiplying digital to analog converter means for multiplying said fourth coefficient signal times said sample first variable signal to produce a fifth analog signal, second summer means for producing a sixth analog signal representing the sum of said fourth and fifth analog signals, analog multiplier means for multiplying said sixth analog signal by said sample second variable signal to produce a seventh analog signal, and third summer means for producing a said continuous analog output signal representing the sum of said third and seventh analog signals, thereby providing said desired function at said selected addresses corresponding to said sample first and second independent variable signals; and wherein said processing means comprises: first buffer storage means for storing said sample first variable signal, second buffer storage means for storing said sample second variable signal, first interpolation means for comparing said sample first variable signal in the first buffer storage means with said stored first independent variable array to determine the address in said stored first independent variable array corresponding to said sample first variable signal, second interpolation means for comparing said sample second variable signal in the second buffer storage means with said stored second independent variable array to determine the address in said stored second independent variable array corresponding to said sample second variable, and coefficient addressor means for combining said determined addresses corresponding to said sample first and second independent variable signals to select the addresses of said corresponding coefficients.
Claim 3
Dependent Claim
102 words
An apparatus according to claim 1, wherein said processing means further comprises: first analog to digital conversion means for converting said sample first variable signal and placing said converted signal in said first buffer storage means; second analog to digital conversion means for converting said sample second variable signal and placing said converted signal in said second buffer storage means; and analog to digital control logic means for initiating said conversion in the first and second analog to digital conversion means and for simultaneously clocking the results of the previous analog to digital conversions into the first and second buffer storage means.
Claim 4
Dependent Claim
35 words
An apparatus according to claim 2, wherein said processing means further comprises: coefficient memory output buffer means interfacing with said function generator means for storing said digital signals representing said coefficients at said selected addresses.
Claim 5
Dependent Claim
80 words
An apparatus according to claim 3 wherein said first and second analog to digital conversion means generate end of conversion pulses that are synchronized by the analog to digital control logic means to form an end of conversion pulse that clocks said signals representing said coefficients into the coefficient memory output buffer means and reinitiates said process of selecting said addresses in said stored arrays of coefficients corresponding to the next input combination of sample first and second variable signals.
Claim 6
Dependent Claim
28 words
An apparatus according to claim 3 wherein the function generator continuously receives the signals in the coefficient memory output buffer means for producing said continuous analog output signal.
Claim 7
Dependent Claim
35 words
An apparatus according to claim 1 further comprising: scaling means for biasing the signals generated by said first summer means and said analog multiplier means prior to applying those signals to said third summer means.
Claim 8
Independent Claim
378 words
A method of generating an analog output signal in accordance with a desired function of at least two independent variables, comprising: storing arrays of a first independent variable, a second independent variable, and first, second, third and fourth coefficients corresponding to combinations of a said first and second independent variables at predetermined intervals; inputting sample first and second independent variable signals; processing said input signals by comparing said sample first and second independent variable signals with said stored first and second independent variable arrays to select addresses in said stored arrays of coefficients corresponding to combinations of said sample independent variable signals; and generating an analog output signal by combining digital signals representing said coefficients at said selected addresses with said sample independent variable signals to produce a continuous analog output signal, said generating step comprising: converting said first coefficient signal into a first analog signal, multiplying said second coefficient signal times said sample first variable signal to produce a second analog signal, producing a third analog signal representing the sum of said first and second analog signals, converting said third coefficient signal into a fourth analog signal, multiplying said fourth coefficient signal times said sample first variable signal to produce a fifth analog signal, producing a sixth analog signal representing the sum of said fourth and fifth analog signals, multiplying said sixth analog signal by said sample second variable signal to produce a seventh analog signal, and producing a said continuous analog output signal representing the sum of the third and seventh analog signals, thereby providing said desired function at said selected addresses corresponding to said sample first and second independent variable signals; and wherein said processing step comprises: storing said sample first variable signal, storing said sample second variable signal, comparing said stored sample first variable signal with said stored first independent variable array to determine the address in said stored first independent variable array corresponding to said sample first variable signal, comparing said stored sample second variable signal with said stored second independent variable array to determine the address in said stored second independent variable array corresponding to said sample second variable, and combining said determined addresses corresponding to said sample first and second independent variable signals to select the addresses of said corresponding coefficients.
Claim 9
Independent Claim
378 words
A method of generating an analog output signal in accordance with a desired function of at least two independent variables, comprising: storing arrays of a first independent variable, a second independent variable, and first, second, third and fourth coefficients corresponding to combinations of a said first and second independent variables at predetermined intervals; inputting sample first and second independent variable signals; processing said input signals by comparing said sample first and second independent variable signals with said stored first and second independent variable arrays to select addresses in said stored arrays of coefficients corresponding to combinations of said sample independent variable signals; and generating an analog output signal by combining digital signals representing said coefficients at said selected addresses with said sample independent variable signals to produce a continuous analog output signal, said generating step comprising: converting said first coefficient signal into a first analog signal, multiplying said second coefficient signal times said sample first variable signal to produce a second analog signal, producing a third analog signal representing the sum of said first and second analog signals, converting said third coefficient signal into a fourth analog signal, multiplying said fourth coefficient signal times said sample first variable signal to produce a fifth analog signal, producing a sixth analog signal representing the sum of said fourth and fifth analog signals, multiplying said sixth analog signal by said sample second variable signal to produce a seventh analog signal, and producing a said continuous analog output signal representing the sum of the third and seventh analog signals, thereby providing said desired function at said selected addresses corresponding to said sample first and second independent variable signals; and wherein said processing step comprises: storing said sample first variable signal, storing said sample second variable signal, comparing said stored sample first variable signal with said stored first independent variable array to determine the address in said stored first independent variable array corresponding to said sample first variable signal, comparing said stored sample second variable signal with said stored second independent variable array to determine the address in said stored second independent variable array corresponding to said sample second variable, and combining said determined addresses corresponding to said sample first and second independent variable signals to select the addresses of said corresponding coefficients.
References Cited (Backward Citations)
US3373273A
Cited
US3480767A
Cited
US3513301A
Cited
US3557347A
Cited
US3678258A
Cited
US3831016A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-12-28 | 1980-06-28 | 1980-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-12-28 | 1984-06-28 | 1984-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-12-28 | 1988-06-28 | 1988-12-28 | $7700.00 | Window Closed / Lapsed |