US3993982A
Expired / Lapsed
US
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Sequence control unit for a television time base corrector
Assignee: J CARL COOPER
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Filing: 1975-01-10
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Granted: 1976-11-23
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Expires: 1995-01-10
Abstract
Abstract A sequence control unit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converted from analog to digital form, temporarily stored in a memory unit at a clocking rate which varies in a manner generally proportional to the time base errors, and the stored signals are fetched at a standard clocking rate. The sequence control unit controls contemporaneous storing and fetching from different portions of the memory unit and includes circuitry for preventing application of both store and fetch signals to the same memory unit portion when the accumulated time base error would cause such an overlap condition.
Inventors
- 👤 Michael W. Tallent
- 👤 Lee E. Scaggs
- 👤 Allan L. Swain
- 👤 Ronnie M. Harrison
- 👤 William B. Hendershot, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:12
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/896; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073; H04N5/0736
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
185 words
A sequence control unit for sequentially enabling a plurality of memory units for contemporaneous store and fetch operations at rates specified by first and second clock signal trains respectively, said sequence unit comprising: write enable means adapted to be coupled to a first reference input signal for sequentially generating mutually exclusively write enable signals each specifying a different one of said memory units for a store operation; means coupled to said write enable means and having an input adapted to be coupled to said first clock signal train for coupling said first clock signal train to different ones of said memory units in accordance with said write enable signals; read enable means adapted to be coupled to a second reference input signal for sequentially generating mutually exclusive read enable signals each specifying a different one of said memory units for a fetch operation; means coupled to said read enable means and having an input adapted to be coupled to said second clock signal train for coupling said second clock signal train to different ones of said memory units in accordance with said read enable signals;
Claim 2
Dependent Claim
185 words
A sequence control unit for sequentially enabling a plurality of memory units for contemporaneous store and fetch operations at rates specified by first and second clock signal trains respectively, said sequence unit comprising: write enable means adapted to be coupled to a first reference input signal for sequentially generating mutually exclusively write enable signals each specifying a different one of said memory units for a store operation; means coupled to said write enable means and having an input adapted to be coupled to said first clock signal train for coupling said first clock signal train to different ones of said memory units in accordance with said write enable signals; read enable means adapted to be coupled to a second reference input signal for sequentially generating mutually exclusive read enable signals each specifying a different one of said memory units for a fetch operation; means coupled to said read enable means and having an input adapted to be coupled to said second clock signal train for coupling said second clock signal train to different ones of said memory units in accordance with said read enable signals;
Claim 3
Dependent Claim
61 words
means for detecting an overlap condition in which said write and read enable signals specify the same one of said memory units for contemporaneous store and fetch operations; and means responsive to said detecting means for presetting said read enable means to generate a read enable signal specifying a different one of said memory units whenever said overlap condition is detected.
Claim 4
Dependent Claim
61 words
means for detecting an overlap condition in which said write and read enable signals specify the same one of said memory units for contemporaneous store and fetch operations; and means responsive to said detecting means for presetting said read enable means to generate a read enable signal specifying a different one of said memory units whenever said overlap condition is detected.
Claim 5
Dependent Claim
45 words
The system of claim 1 wherein said read enable means include a counter for dividing said second reference input signal to define a fetch interval, and said presetting means includes means for presetting said counter to a state defining a fraction of said fetch interval.
Claim 6
Dependent Claim
10 words
The system of claim 2 wherein said fraction is 1/3.
References Cited (Backward Citations)
US3812473A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-11-23 | 1980-05-24 | 1980-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-11-23 | 1984-05-24 | 1984-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-11-23 | 1988-05-24 | 1988-11-23 | $7700.00 | Window Closed / Lapsed |