Multi-frequency range operation of a network analyzer system

Claim 3

The system as in claim 1, further comprising: a display device coupled to the network analyzer to receive data therefrom; and means coupled to the interface circuit and the display device for providing a fourth electrical signal in response to the third electrical signal, the display device suspending operation in response to the fourth electrical signal.

Claim 4

The system as in claim 2, wherein the sweep oscillator has a first and second frequency range between the first and second frequencies and provides a fifth electrical signal when the first electrical signal passes from the first frequency range to the second frequency range.

Claim 5

The system as in claim 3, wherein the sweep oscillator also provides the fifth electrical signal in response to the finish of a retrace operation.

Claim 6

The system as in claim 3, wherein the phase-lock loop circuit comprises a voltage-tuned oscillator and the interface circuit comprises: means for responding to an unlocked state in said phase-lock loop circuit and for providing a control signal in response thereto; means for detecting when an upper limit is reached by the voltage-tuned oscillator in said phase-lock loop and providing a sixth electrical signal when the upper limit is reached; a first one-shot circuit coupled to the means for detecting for providing a first enable signal in response to the fifth electrical signal and to the sixth electrical signal; and gating means coupled to the first one-shot and the means for responding for producing the third electrical signal in response to the simultaneous presence of the enable signal and the control signal.

Claim 7

The system as in claim 5, wherein the interface circuit further comprises: a second one-shot circuit coupled to the means for detecting for providing a second enable signal in response to the fifth and sixth electrical signals; and a programmable circuit for providing signals representing a loop gain compensation value and a frequency range for said phase-lock loop circuit in response to the second electrical signal and the second enable signal.

Claim 8

The system as in claim 6, wherein the interface circuit further includes a third one-shot circuit coupled to the means for responding for providing a third enable signal in response to the fifth and sixth electrical signals, a break lock circuit for causing said phase-lock loop circuit to lose phase-lock in response to the third enable signal, and a search initialize circuit for causing the voltage-tuned oscillator in said phase-lock loop circuit to be tuned to a starting frequency in response to the third enable signal.

Claim 9

A network analyzer comprising: first input means for receiving a first electrical signal progressing from a first frequency to a second frequency; second input means for receiving a second electrical signal which is related to the frequency of the first signal; a phase-lock loop circuit having a voltage-tuned oscillator and coupled to the first and second input means to receive the first and second electrical signals and for phase-locking on the first electrical signal in response to the second electrical signal; and an interface circuit coupled to the phase-lock loop circuit for providing a third electrical signal when the phase-lock loop circuit is not locked on the first electrical signal.

Claim 10

A network analyzer comprising: first input means for receiving a first electrical signal progressing from a first frequency to a second frequency; second input means for receiving a second electrical signal which is related to the frequency of the first signal; a phase-lock loop circuit having a voltage-tuned oscillator and coupled to the first and second input means to receive the first and second electrical signals and for phase-locking on the first electrical signal in response to the second electrical signal; and an interface circuit coupled to the phase-lock loop circuit for providing a third electrical signal when the phase-lock loop circuit is not locked on the first electrical signal.

Claim 11

The network analyzer as in claim 8, wherein the network analyzer further comprises an interface circuit comprising: means coupled to the phase-lock loop circuit for responding to an unlocked state in said phase-lock loop circuit and for providing a control signal in response thereto; means coupled to the phase-lock loop circuit for detecting when an upper limit is reached by the voltage-tuned oscillator in said phase-lock loop circuit and for providing a sixth electrical signal when the upper limit is reached; a first one-shot circuit coupled to the means for detecting for providing a first enable signal in response to the fifth electrical signal; and gating means coupled to the first one-shot and to the means for responding for producing the third electrical signal is response to the simultaneous presence of the enable signal and the control signal.

Claim 12

The network analyzer as in claim 9, wherein the phase-lock loop includes a circuit for providing loop gain compensation in response to a signal representing a loop gain compensation value, and a search oscillator for tuning said voltage-tuned oscillator in response to a signal representing a frequency range; and wherein the interface circuit further comprises a second one-shot circuit coupled to the means for detecting for providing a second enable signal in response to the fifth and sixth electrical signals, a programmable circuit coupled to the phase-lock loop for providing the signal representing a loop gain compensation value and the signal representing a frequency range for said search oscillator in response to the second electrical signal and the second enable signal.

Claim 13

The network analyzer as in claim 10, wherein the interface circuit further comprises: a third one-shot circuit coupled to the means for responding for providing a third enable signal in response to the fifth and sixth electrical signals; a break lock circuit coupled to the phase-lock loop circuit for causing said phase-lock loop circuit to lose phase-lock in response to the third enable signal; and a search initialize circuit coupled to the phase-lock loop circuit for causing the voltage-tuned oscillator in said phase-lock loop circuit to be tuned to a starting frequency in response to the third enable signal.