US3989962A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Negative-resistance semiconductor device
Assignee: Panasonic Holdings Corp
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Filing: 1975-03-05
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Granted: 1976-11-02
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Expires: 1995-03-05
Abstract
Abstract Both source-electrodes (S1 and S2) or both drain-electrodes of a pair of field-effect transistors (FETs) (F1 and F2) of n-channel type and p-channel type, respectively, both to be electrically actuated in a depletion mode are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, through a variable resistance element (F3) inbetween, whereby the pair of FETs (F1 and F3) are series-connected through the variable resistance element (F3) inbetween, the gate-electrode (g1 or g2) of each FET is connected to the drain-electrode (d2 or d1) or the source-electrode of the other FET (F2 or F1) that is not connected to the variable resistance element (F3), and a pair of external terminals (1 and 2) are connected to said gate electrodes (g1, g2) those are connected to said drain electrodes (d2 and d1) or source electrodes. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon, and a curve of voltage-current characteristic changes responding to the value of control signal to the variable resistance element. Since this device is a negative resistance of variable characteristic this device can be utilized for switching, signal relaying, memorization and other various controlling or data processing uses.
Inventors
- 👤 Hiromitsu Takagi
- 👤 Gota Kano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:01
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/082; H03K17/0826; H02; H02H; H02H9/00; H02H9/02; H02H9/025
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
209 words
A two terminal negative resistance device having first and second external terminals and capable of continuously changing its negative resistance characteristic, comprising a complementary pair of transistors comprising a depletion mode n-channel unipolar transistor and a depletion mode p-channel unipolar transistor, an active circuit element having at least two terminals and an input and functioning to change its resistance between said two terminals in response to an input signal, each of said unipolar transistors having a gate and a pair of source-drain output circuit terminals, one of the output circuit terminals of said p-channel unipolar transistor being connected by a first connection to one of said two terminals of said active circuit element, one of the output circuit terminals of said n-channel unipolar transistor being connected by a second connection to the other of said two terminals of said active circuit element, the gates of each of said unipolar transistors being connected by respective third and fourth connections to the other output circuit terminal of the other unipolar transistor, and said third and fourth connections being respectively connected to said first and second external terminals, whereby changing resistance of the active circuit element in response to an input signal changes the negative resistance characteristic of said negative resistance device.
Claim 2
Dependent Claim
209 words
A two terminal negative resistance device having first and second external terminals and capable of continuously changing its negative resistance characteristic, comprising a complementary pair of transistors comprising a depletion mode n-channel unipolar transistor and a depletion mode p-channel unipolar transistor, an active circuit element having at least two terminals and an input and functioning to change its resistance between said two terminals in response to an input signal, each of said unipolar transistors having a gate and a pair of source-drain output circuit terminals, one of the output circuit terminals of said p-channel unipolar transistor being connected by a first connection to one of said two terminals of said active circuit element, one of the output circuit terminals of said n-channel unipolar transistor being connected by a second connection to the other of said two terminals of said active circuit element, the gates of each of said unipolar transistors being connected by respective third and fourth connections to the other output circuit terminal of the other unipolar transistor, and said third and fourth connections being respectively connected to said first and second external terminals, whereby changing resistance of the active circuit element in response to an input signal changes the negative resistance characteristic of said negative resistance device.
Claim 3
Dependent Claim
51 words
A negative resistance device according to claim 1 wherein said active circuit element comprises a field-effect transistor whose source and drain terminals constitute said two terminals, and the gate of which comprises an input to which an input signal can be applied for changing the resistance of said active circuit element.
Claim 4
Dependent Claim
30 words
A negative resistance device as claimed in claim 1, wherein said unipolar transistors and said active circuit element are formed in a single monolithic wafer to constitute an integrated circuit.
Claim 5
Dependent Claim
16 words
The negative resistance device of claim 1, wherein said active circuit element is a bi-polar transistor.
Claim 6
Dependent Claim
15 words
The negative resistance device of claim 1, wherein said active circuit element is a phototransistor.
Claim 7
Dependent Claim
18 words
The negative resistance device of claim 1, wherein said active circuit element is a force sensitive semiconductor element.
Claim 8
Dependent Claim
17 words
The negative resistance of claim 1, wherein said active circuit element is a magnetic-field sensitive semiconductor element.
Claim 9
Dependent Claim
169 words
A negative resistance device comprising a unipolar transistor having gate, source and drain electrodes and a unipolar tetrode transistor having source, drain, and first and second gate electrodes, channel-conductivities of the unipolar transistor and that of the unipolar tetrode transistor being opposite to each other, one of the source and drain electrodes of said unipolar transistor being connected to one of the source and drain electrodes of said unipolar tetrode transistor, the gate electrode of said unipolar transistor and one of the gate electrodes of said unipolar tetrode transistor being connected to the other of the source and drain electrodes of said unipolar tetrode transistor and said unipolar transistor, respectively, the other gate electrode of said unipolar tetrode transistor being connected to a control terminal to which a control voltage can be applied, and a pair of external terminals being connected to said other of the source and drain electrodes of said unipolar transistor and said other of the source and drain electrodes of said unipolar tetrode transistor, respectively.
Claim 10
Dependent Claim
169 words
A negative resistance device comprising a unipolar transistor having gate, source and drain electrodes and a unipolar tetrode transistor having source, drain, and first and second gate electrodes, channel-conductivities of the unipolar transistor and that of the unipolar tetrode transistor being opposite to each other, one of the source and drain electrodes of said unipolar transistor being connected to one of the source and drain electrodes of said unipolar tetrode transistor, the gate electrode of said unipolar transistor and one of the gate electrodes of said unipolar tetrode transistor being connected to the other of the source and drain electrodes of said unipolar tetrode transistor and said unipolar transistor, respectively, the other gate electrode of said unipolar tetrode transistor being connected to a control terminal to which a control voltage can be applied, and a pair of external terminals being connected to said other of the source and drain electrodes of said unipolar transistor and said other of the source and drain electrodes of said unipolar tetrode transistor, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-11-02 | 1980-05-03 | 1980-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-11-02 | 1984-05-03 | 1984-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-11-02 | 1988-05-03 | 1988-11-02 | $7700.00 | Window Closed / Lapsed |