Charge transfer binary counter

Claim 2

In a charge transfer binary counter for counting the number of signal pulses in a particular time interval up to a maximum of 2 n - 1 pulses in the interval, a device comprising: a charge storage medium, a quantizer comprising first electrode means for forming in said medium at least one charge storage cell adapted to generate a predetermined packet of charge in response to each of said signal pulses, second electrode means for forming in said tandem medium a plurality n of charge storage threshold cells coupled in tandem with one another and at least one of which is disposed to receive charge transferred out of said quantizer, means for applying clock voltages to said first and second electrode means, each of said threshold cells having at its input a first potential barrier across which virtually all charge transferred out of a preceding cell will transfer into said threshold cell upon the application of clock voltage from said applying means to said second electrode means and having at its output a second potential barrier, the area of each threshold cell and the height of its second barrier being mutually adapted in relation to the clock voltage so that charge transfer across the second barrier occurs only when two of said charge packets are transferred into said threshold cell, and feeback means responsive to charge transferred across any of the first (n-1) of said second barriers for removing residual charge remaining in the corresponding threshold cells.

Claim 3

The device of claim 1 wherein the source of said signal pulses is such that a quasi-steady-state condition is reached during which no additional signal pulses are applied to said quantizer and said clock voltage applying means is effective to cause charge transferred across said threshold barriers to be further transferred into the next succeeding threshold cells, and including means for detecting the presence or absence of such charge in each of said threshold cells, which correspond to the k th binary digit having the decimal equivalent 2 k -1 .

Claim 4

The device of claim 1 wherein said feedback means includes third electrode means for forming in said medium a plurality of charge storage transfer cells, a transfer cell being positioned between each pair of threshold cells so that charge transferred across the threshold barrier of the preceding cell is collected by the transfer cell, and control means responsive to charge transferred into said transfer cells for removing residual charge remaining in the threshold cells.

Claim 5

The device of claim 3 wherein said control means includes dump gate electrode means for forming in said medium a plurality of n charge storage dump cells which are adjacent to separate ones of said n threshold cells, a plurality of insulated gate field effect transistors each having source, drain and gate electrodes, the gate electrodes being coupled to respective ones of at least the first (n-1) of said transfer cells and the source or drain electrodes being coupled to respective ones of at least the first (n-1) of said dump cells, and means for dissipating charge transferred into said dump cells in response to the activation of said transistors by the presence of charge in said transfer cells.

Claim 6

The device of claim 4 wherein said charge storage medium includes a semiconductor substrate and an insulative layer formed on a major surface thereof, said electrode means being formed on said insulative layer, said transistors having their source electrodes connected to said substrate and their drain electrodes coupled to respective ones of said dump cells, and said dissipating means comprises a second plurality of insulated gate field effect transistors each having source, drain and gate electrodes, each gate electrode being connected to its drain electrode which is in turn connectable to a source of voltage bias and each source electrode being coupled to a dump cell.

Claim 7

The device of claim 4 including a clock cycle counter, read means responsive to said clock cycle counter for activating said dump cells so that charge in said threshold cells is transferred into said dump cells at the end of said time interval, the presence or absence of charge in the k th one of said dump cells corresponding to the k th binary digit having a decimal equivalent 2 k - 1 .

Claim 8

The device of claim 6 wherein said applying means comprises a two-phase clock voltage means, and including means for coupling alternate ones of said quantizer cells, threshold cells and transfer cells to opposite phases of said clock means.

Claim 9

The device of claim 7 wherein said quantizer has an even number of storage cells and said clock cycle counter activates said read means after an integral number of clock cycles.

Claim 10

The device of claim 7 wherein said quantizer has an odd number of storage cells and said clock cycle counter activates said read means after an odd integral number of half clock cycles.

Claim 11

The device of claim 1 wherein said quantizer-cells each have an area A, said threshold cels each have an area 2A and said second barriers are approximately 1.5 times as large as said first barriers.

Claim 12

The device of claim 10 wherein said applying means comprises two-phase voltage clock means, and including means for coupling alternate ones of said quantizer cells to opposite phases of said clock means and for coupling all of said threshold cells to the same phase of said clock means, and wherein the voltage swing of said clock means is equal approximately to the height of said first barriers.

Claim 13

in a charge transfer binary counter for counting the number of signal pulses in a particular time interval up to a maximum of 2 n - 1 pulses in the interval, a device comprising: a charge storage medium, a quantizer comprising first electrode means for forming in said medium at least one charge storage cell adapted to generate a predetermined packet of charge in response to each of said signal pulses, second electrode means for forming in said medium at least (n-1) shift registers coupled in tandem to one another, means for applying clock voltages to said first and second electrode means, each of said shift registers comprising a charge storage threshold cell and contiguous thereto a charge storage transfer cell, a first potential barrier being located at the input to each threshold cell and a second potential barrier being located at the interface between said threshold and transfer cells, said first barrier adapted to permit virtually complete charge transfer thereacross in response to clock voltage applied thereto from said applying means, and the area of each threshold cell and the height of its second barrier being mutually adapted in relation to the clock voltage so that charge transfers thereacross only if two of said charge packets are transferred into said threshold cell. each of said shift registers further including feedback means responsive to charge transferred across its second barrier for removing charge remaining in its threshold cell, and a terminal threshold cell coupled to the output of the (n-1) th shift register, another of said second barriers being located at the output of said terminal cell.

Claim 14

in a charge transfer binary counter for counting the number of signal pulses in a particular time interval up to a maximum of 2 n - 1 pulses in the interval, a device comprising: a charge storage medium, a quantizer comprising first electrode means for forming in said medium at least one charge storage cell adapted to generate a predetermined packet of charge in response to each of said signal pulses, second electrode means for forming in said medium at least (n-1) shift registers coupled in tandem to one another, means for applying clock voltages to said first and second electrode means, each of said shift registers comprising a charge storage threshold cell and contiguous thereto a charge storage transfer cell, a first potential barrier being located at the input to each threshold cell and a second potential barrier being located at the interface between said threshold and transfer cells, said first barrier adapted to permit virtually complete charge transfer thereacross in response to clock voltage applied thereto from said applying means, and the area of each threshold cell and the height of its second barrier being mutually adapted in relation to the clock voltage so that charge transfers thereacross only if two of said charge packets are transferred into said threshold cell. each of said shift registers further including feedback means responsive to charge transferred across its second barrier for removing charge remaining in its threshold cell, and a terminal threshold cell coupled to the output of the (n-1) th shift register, another of said second barriers being located at the output of said terminal cell.

Claim 15

The device of claim 12 wherein the source of said signals is such that a quasi-steady-state condition is reached during which no additional signal pulses are applied to said quantizer, and said clock voltage applying means is effective to cause charge transferred across the threshold barriers of said shift registers to be further transferred into the next succeeding threshold cells, and including means for detecting the presence or absence of charge in the k th one of said threshold cells, including said terminal cell, which corresponds to the k th binary digit having the decimal equivalent 2 k -1 .

Claim 16

The device of claim 13 wherein said detecting means includes electrode means for forming a plurality n of charge storage dump cells coupled to separate ones of said threshold cells, a clock cycle counter, read means responsive to said clock cycle counter for activating said dump cells so that charge is transferred from said threshold cells into said dump cells.

Claim 17

The device of claim 14 wherein said applying means comprises two-phase clock voltage means and wherein said quantizer cells, threshold cells and transfer cells are coupled to opposite phases of said clock means.

Claim 18

The device of claim 14 wherein said feedback means includes in each shift register an insulated gate field effect transistor having source, drain and gate electrodes, the gate electrode being coupled to the transfer cell and one of the source or drain electrodes being coupled to the dump gate adjacent its threshold cell, and means for dissipating charge transferred into said dump cells in response to activation of said transistors by the presence of charge in said transfer cells.

Claim 19

The device of claim 12 wherein said quantizer cells each have an area A, said threshold cells of said shift registers each have an area 2A, and said second barriers are approximately 1.5 times as large as said first barrier.

Claim 20

The device of claim 17 wherein said applying means comprises two-phase clock voltage means, and including means for coupling alternate ones of said quantizer cells, threshold cells, and transfer cells to opposite phases of said clock means, and wherein the voltage swing of said clock means is equal approximately to the height of said first barriers.