US3989892A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Line concentrator for dealing with asynchronous and synchronous data signals in a common bit format for a time division data switching exchange
Assignee: Fujitsu Ltd
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Filing: 1975-07-03
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Granted: 1976-11-02
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Expires: 1995-07-03
Abstract
Abstract A line concentrator for a time division data switching exchange. Asynchronous and synchronous data signals generated at asynchronous and synchronous data terminals are subjected to known multi-point and synchronous sampling to become a train of bit-multiplexed first asynchronous and synchronous data channel signals. Responsive to a train of bit-interleaved read-in pulse groups timed relative to the respective synchronous data signals, an arithmetic unit stores the data channel signals in an octet memory according to the asynchronous and synchronous data terminals. Responsive to a train of read-out pulses appearing for the respective data terminals, the arithmetic unit reproduces groups of uninterleaved data channel signals for each data terminal and composes the reproduced data channel signals into a train of second asynchronous and synchronous data channel signals given by a common and uninterleaved bit format. The line concentrator is readily modified for decomposition of a train of asynchronous and synchronous data channel signal groups of the bit format into replicas of the original data signals.
Inventors
- 👤 Shinichiro Yoshida
- 👤 Yoshitsugu Watanabe
- 👤 Yuji Hayano
- 👤 Susumu Ohara
- 👤 Takuhito Kojima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:31
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/22; H04L5/24; H04L12/00; H04L12/50; H04L12/52; H04L12/525
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
229 words
A line concentrator for use between a highway for a time division data switching exchange and a plurality of asynchronous and synchronous data terminals for asynchronous and synchronous data signals, each comprising a series of bits, said synchronous data signals having a common bit frequency, said line concentrator comprising: first means responsive to a first set of timing pulse trains for effecting conversion between said asynchronous data signals and first asynchronous data channel signals of a first time division multiplexed signal train at a plurality of time positions in each bit of said asynchronous data signals, second means responsive to a second set of timing pulse trains having a common repetition frequency of an integral multiple of said bit frequency and timed relative to said first set of timing pulse trains for effecting conversion between said synchronous data signals and first synchronous data channel signals of said first time division multiplexed signal train, third means for carrying out conversion between said first asynchronous and synchronous data channel signals and second asynchronous and synchronous data channel signals of a second time division multiplexed signal train, and fourth means for transmitting said second time division multiplexed signal train between said third means and said highway, said second asynchronous and synchronous data channel signals having bit structures of a common and uninterleaved bit format of (x+2)-bit envelope, where x represents an integer.
Claim 2
Dependent Claim
229 words
A line concentrator for use between a highway for a time division data switching exchange and a plurality of asynchronous and synchronous data terminals for asynchronous and synchronous data signals, each comprising a series of bits, said synchronous data signals having a common bit frequency, said line concentrator comprising: first means responsive to a first set of timing pulse trains for effecting conversion between said asynchronous data signals and first asynchronous data channel signals of a first time division multiplexed signal train at a plurality of time positions in each bit of said asynchronous data signals, second means responsive to a second set of timing pulse trains having a common repetition frequency of an integral multiple of said bit frequency and timed relative to said first set of timing pulse trains for effecting conversion between said synchronous data signals and first synchronous data channel signals of said first time division multiplexed signal train, third means for carrying out conversion between said first asynchronous and synchronous data channel signals and second asynchronous and synchronous data channel signals of a second time division multiplexed signal train, and fourth means for transmitting said second time division multiplexed signal train between said third means and said highway, said second asynchronous and synchronous data channel signals having bit structures of a common and uninterleaved bit format of (x+2)-bit envelope, where x represents an integer.
Claim 3
Dependent Claim
253 words
A line concentrator as claimed in claim 1, further comprising timing pulse producing means for producing said first and second timing pulse trains, and wherein said third means comprises: read-in signal producing means operatively coupled to said timing pulse producing means for producing read-in signals in synchronism with said first and second timing pulse trains, read-out signal producing means for producing read-out signals indicative of time slots assigned in said second time division multiplexed signal train to the respective asynchronous and synchronous data terminals, memory means having memory locations assigned to the respective asynchronous and synchronous data terminals, each of said memory locations being capable of memorizing a predetermined number of said first asynchronous and synchronous data channel signals, and arithmetic unit means for storing in response to said read-in signals said first asynchronous and synchronous data channel signals in the memory locations assigned to the respective asynchronous and synchronous data terminals, for producing in response to the read-out signals indicative of the time slots for said asynchronous data terminals the first asynchronous data channel signals, x bits in number, from each of the relevant memory locations, for adding data channel signals for 2 bits to the produced x-bit first asynchronous data channel signals to thereby form said second asynchronous data channel signals, and for producing in response to the read-out signals for said synchronous data terminals the first synchronous data channel signals, x+2 bits in number, from each of the relevant memory locations to thereby form said second synchronous data channel signals.
Claim 4
Dependent Claim
227 words
A line concentrator as claimed in claim 1, further comprising timing pulse producing means for producing said first and second timing pulse trains, and wherein said third means comprises: means responsive to said second time division multiplexed signal train for producing timing signals indicative of time slots assigned in said second time division multiplexed signal train to the respective asynchronous and synchronous data terminals, read-out signal producing means operatively coupled to said timing pulse producing means for producing read-out signals in synchronism said first and second timing pulse trains, memory means having memory locations assigned to the respective asynchronous and synchronous data terminals, each of said memory locations being capable of memorizing a predetermined number of said second asynchronous and synchronous data channel signals, and arithmetic unit means for storing in response to said timing signals the second asynchronous data channel signals, x bits in number among the x+2 bits, in one of said memory locations assigned to the x-bit second asynchronous data channel signals, for storing in response to said timing signals the second synchronous data channel signals, x+2 bits in number, in one of said memory locations assigned to the (x+2)-bit second synchronous data channel signals, and for producing in response to said read-out signals the second asynchronous and synchronous data channels from said memory locations as said first asynchronous and synchronous data channel signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-11-02 | 1980-05-03 | 1980-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-11-02 | 1984-05-03 | 1984-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-11-02 | 1988-05-03 | 1988-11-02 | $7700.00 | Window Closed / Lapsed |