Integrated injection logic random access memory

Claim 2

A semiconductor memory cell formed on a common emitter region of one polarity semiconductor material having a memory access control circuit for providing a first voltage arbitrarily designated as a binary 1 and a second voltage arbitrarily designated as a binary 0 to provide a holding mode, a write mode, and a read mode, and having first and second vertical transistors of one polarity type, their emitters being integral with the common emitter region, electrically connected to form a latch circuit for setting the latch circuit in an arbitrarily designated 0 state by injecting current into the base of the first vertical transistor causing it to conduct and causing the second vertical transistor to be cut off and for setting the latch circuit in an arbitrarily designated 1 state by injecting current into the base of the second vertical transistor causing it to conduct and causing the first vertical transistor to be cut off, comprising: a. holding injection circuit means connected to the control circuit and the latch circuit for maintaining current injection into the base of the conducting first or second transistor during the holding mode; b. read-out means operatively connected to the control circuit and connected to the latch circuit for providing an indication of the binary state of the latch circuit; and c. write and read injection circuit means connected to the control circuit for selectively injecting current into the base of the conducting first or second vertical transistor to set the latch circuit in the 0 or 1 state respectively during the write mode, and for maintaining current injection into the base of the conducting first or second vertical transistor during the read mode.

Claim 3

The memory cell of claim 1 wherein the read-out means comprise a vertical output transistor of the one conductivity type its emitter being integral with the common emitter region, its base being connected to the collector of the second transistor and its collector providing the indication of the binary state of the latch circuit.

Claim 4

The memory cell of claim 2 wherein the write and read injection means further comprise: c. i. a first lateral transistor of the opposite conductivity type, having its emitter connected to the control circuit, its base integral with the common emitter region and its collector connected to the base of the second vertical transistor; and ii. a second lateral transistor of the opposite conductivity type, having its emitter connected to the control circuit, its base integral with the common emitter region, a first collector connected to the base of the first vertical transistor and the second collector connected to the base of the output transistor for providing base drive thereto.

Claim 5

The memory cell of claim 3 wherein the holding injection circuit means further comprise: a. i. a word select line formed in the common emitter region of the opposite polarity semiconductor material, connected to the control means; and ii. a third lateral transistor having its emitter integral with the work select line, its base integral with the common emitter region, one collector integral with the base of the first vertical transistor and another collector integral with the base of the second transistor.

Claim 6

The memory cell of claim 4 wherein the read-out means further comprise a vertical read-out transistor having its base integral with the word select line, its emitter integral with the common emitter region and its collector connected to the base of the output transistor.

Claim 7

The memory cell of claim 5 wherein the collector of the first lateral transistor is integral with the base of the second vertical transistor and the collector of the second lateral trnasistor is integral with the base of the first vertical transistor.

Claim 8

The memory cell of claim 2 wherein the write and read injection circuit means further comprise: c. i. a first lateral transistor of the opposite conductivity type, having its emitter connected to the control circuit, its base integral with the common emitter region and its collector connected to the base of the second vertical transistor; ii. a second lateral transistor of the opposite conductivity type having its emitter connected to the control circuit, its base integral with the common emitter region and its collector connected to the base of the first vertical transistor; and iii. a third lateral transistor having its emitter connected to the control circuit, its base integral with the common emitter region, one collector integral with the base of the first vertical transistor, one collector integral with the base of the second vertical transistor and a third collector integral with the base of the output transistor to provide base drive thereto.

Claim 9

The memory cell of claim 7 wherein the holding injection circuit means further comprise: a. i. a word select line formed in the common emitter region of the opposite polarity semiconductor material, connected to the control means; and ii. a fourth lateral transistor having its emitter integral with the word select line, its base integral with the common emitter region, one collector integral with the base of the first vertical transistor and another collector integral with the base of the second vertical transistor.

Claim 10

The memory cell of claim 8 wherein the read-out means further comprise a vertical read-out transistor having its base integral with the word select line, its emitter integral with the common emitter region and its collector connected to the base of the output transistor.

Claim 11

The memory cell of claim 9 wherein the collector of the first lateral transistor is integral with the base of the second vertical transistor and the collector of the second lateral transistor is integral with the base of the first vertival transistor.

Claim 12

The memory cell of claim 2 wherein the write and read injection circuit means further comprise: c. (i) a first lateral transistor of the opposite conductivity type having its emitter connected to the control circuit, its base integral with the common emitter region and its collector connected to the base of the second vertical transistor. ii. a second lateral transistor of the opposite conductivity type having its emitter connected to the control circuit, its base integral with the common emitter region and its collector connected to the base of the first vertical transistor; and iii. a third lateral transistor having its emitter integral with the base of the first vertical transistor, its base integral with the common emitter region and its collector integral with the base of the output transistor to provide base drive thereto.

Claim 13

The memory cell of claim 11 wherein the holding injection circuit means further comprise: a. i. a word select line formed in the common emitter region of the opposite polarity semiconductor material, connected to the control means; and ii. a fourth lateral transistor having its emitter integral with the word select line, its base integral with the common emitter region, one collector integral with the base of the vertical transistor and another collector integral with the base of the second vertical transistor.

Claim 14

The memory cell of claim 12 wherein the read-out means further comprise a vertical read-out transistor having its base integral with the word select line, its emitter integral with the common emitter region and its collector connected to the base of the output transistor.

Claim 15

The memory cell of claim 13 wherein the collector of the first lateral transistor is integral with the base of the second vertical transistor and the collector of the second lateral transistor is integral with the base of the first vertical transistor.

Claim 16

In a memory system having an array of semiconductor memory cells arranged in columns and rows on a common emitter region of one polarity semiconductor material, a plurality of word lines of the other polarity semiconductor material formed in the common emitter region and each word line being attached to each cell in a respective row, a plurality of conductive, column select lines, at least three column select lines being attached to each cell in a column, and a memory access control circuit for selecting a word select line and three column select lines to select a particular cell and to provide thereto a first voltage arbitrarily designated as a binary 1 and a second voltage arbitrarily designated as a binary 0 to provide a holding mode, a write mode, and a read mode, each cell having first and second vertical transistors of one polarity type, their emitters being integral with the common emitter region, electrically connected to form a latch circuit for setting the latch circuit in an arbitrarily designated 0 state by injecting current into the base of the first vertical transistor causing it to conduct and causing the second vertical transistor to be cut off and for setting a latch circuit in an arbitrarily designated 1 state by injecting current into the base of the second vertical transistor causing it to conduct and causing the first vertical transistor to be cut off, each cell comprising: a. a holding injection lateral transistor of the opposite conductivity type having its emitter integral with the corresponding word select line, its base integral with the common emitter region, a first collector integral with the base of the second vertical transistor and a second collector integral with the base of the first vertical transistor. b. read-out means connected to the first of the three corresponding column select lines and connected to the latch circuit for providing an indication of the binary state of the latch circuit; and c. write and read injection circuit means connected to the second and third column select lines for selectively injecting current into the base of the conducting first or second vertical transistor to set the latch circuit in the 0 or 1 state, respectively, during the write mode, and for maintaining current injection into the base of the conducting first or second vertical transistor during the read mode.

Claim 17

In a memory system having an array of semiconductor memory cells arranged in columns and rows on a common emitter region of one polarity semiconductor material, a plurality of word lines of the other polarity semiconductor material formed in the common emitter region and each word line being attached to each cell in a respective row, a plurality of conductive, column select lines, at least three column select lines being attached to each cell in a column, and a memory access control circuit for selecting a word select line and three column select lines to select a particular cell and to provide thereto a first voltage arbitrarily designated as a binary 1 and a second voltage arbitrarily designated as a binary 0 to provide a holding mode, a write mode, and a read mode, each cell having first and second vertical transistors of one polarity type, their emitters being integral with the common emitter region, electrically connected to form a latch circuit for setting the latch circuit in an arbitrarily designated 0 state by injecting current into the base of the first vertical transistor causing it to conduct and causing the second vertical transistor to be cut off and for setting a latch circuit in an arbitrarily designated 1 state by injecting current into the base of the second vertical transistor causing it to conduct and causing the first vertical transistor to be cut off, each cell comprising: a. a holding injection lateral transistor of the opposite conductivity type having its emitter integral with the corresponding word select line, its base integral with the common emitter region, a first collector integral with the base of the second vertical transistor and a second collector integral with the base of the first vertical transistor. b. read-out means connected to the first of the three corresponding column select lines and connected to the latch circuit for providing an indication of the binary state of the latch circuit; and c. write and read injection circuit means connected to the second and third column select lines for selectively injecting current into the base of the conducting first or second vertical transistor to set the latch circuit in the 0 or 1 state, respectively, during the write mode, and for maintaining current injection into the base of the conducting first or second vertical transistor during the read mode.

Claim 18

The memory system of claim 15 wherein the read-out means of each cell further comprise: b. i. a vertical output transistor of the one conductivity type, its emitter being integral with the common emitter region, its base being connected to the collector of the second vertical transistor and its collector providing the indication of the binary state of the latch circuit; and ii. a vertical read-out transistor of the one conductivity type, having its base integral with the corresponding word select line, its emitter integral with the common emitter region and its collector connected to the base of the output transistor.

Claim 19

The memory system of claim 16 wherein the write and read injection means further comprise: c. i. a first lateral transistor of the opposite conductivity type having its emitter connected to the second column select line, its base integral with the common emitter region and its collector integral with the base of the second vertical transistor; and ii. a second lateral transistor of the opposite conductivity type having its emitter connected to the third column select line, its base being integral with the common emitter region, a first collector integral with the base of the first vertical transistor and a second collector being integral with the base of the output transistor for providing base drive thereto.

Claim 20

The memory system of claim 16 wherein the write and read injection means further comprise: c. i. a first lateral transistor of the opposite conductivity type having its emitter connected to the second select line, its base integral with the common emitter region and its collector connected to the base of the second vertical transistor; ii. a second lateral transistor of the opposite conductivity type having its emitter connected to the first column select line, its base integral with the common emitter region and its collector connected to the base of the first vertical transistor; and iii. a third lateral transistor having its emitter connected to the third column select line, its base integral with the common emitter region, one collector integral with the base of the first vertical transistor, one collector integral with the base of the second vertical transistor and the third collector integral with the base of the output transistor to provide base drive thereto.

Claim 21

The memory system of claim 16 wherein the write and read injection circuit means of each cell further comprise: c. i. a first lateral transistor of the opposite conductivity type having its emitter connected to the second column select line, its base integral with the common emitter region and its collector connected to the base of the second vertical transistor; ii. a second lateral transistor of the opposite conductivity type having its emitter connected to the third column select line, its base integral with the common emitter region and its collector connected to the base of the first vertical transistor; and iii. a third lateral transistor having its emitter integral with the base of the first vertical transistor, its base integral with the common emitter region and its collector integral with the base of the output transistor to provide base drive thereto.