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US3986132A Expired / Lapsed US ⏱️ 0.0 years remaining

Series energized transistor amplifier

Assignee: RCA Corp
•
Filing: 1975-10-22
•
Granted: 1976-10-12
•
Expires: 1995-10-22
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Abstract

Abstract A plurality of transistors are connected in series together with a load across a source of operating potential. A primary bias circuit coupled to the transistors apportions the voltage across each transistor under quiescent conditions. A supplementary bias circuit, activated when the potential across one of the transistors is within a given range, supplies additional bias to other of the transistors of the series circuit.

Inventors

  • 👤 Harold Allen Wittlinger

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 05:23
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/42; H03F3/423

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 172 words
In combination: a first transistor and at least one further transistor, each having a conduction path and a control electrode, said conduction paths being connected in series between first and second terminals for conducting a load current therebetween; means for applying a control signal to the control electrode of said first transistor for controlling the flow of said load current; first bias means coupled to the control electrode of said further transistor for supplying a quiescent forward bias thereto; means for applying a reference potential to said first terminal; a third terminal for receiving a source of operating potential; a load connected between said second and third terminals; a current mirror amplifier having input, common and output terminals, said common terminal for connection to a source of potential intermediate said reference and operating potentials, said output terminal being coupled to said control electrode of said further transistor; and circuit means for applying an input current to said input terminal inversely proportional to a voltage across the conduction path of said first transistor.
Claim 2
Dependent Claim 172 words
In combination: a first transistor and at least one further transistor, each having a conduction path and a control electrode, said conduction paths being connected in series between first and second terminals for conducting a load current therebetween; means for applying a control signal to the control electrode of said first transistor for controlling the flow of said load current; first bias means coupled to the control electrode of said further transistor for supplying a quiescent forward bias thereto; means for applying a reference potential to said first terminal; a third terminal for receiving a source of operating potential; a load connected between said second and third terminals; a current mirror amplifier having input, common and output terminals, said common terminal for connection to a source of potential intermediate said reference and operating potentials, said output terminal being coupled to said control electrode of said further transistor; and circuit means for applying an input current to said input terminal inversely proportional to a voltage across the conduction path of said first transistor.
Claim 3
Dependent Claim 110 words
The combination recited in claim 1: further including a plurality of said further transistors, the conduction paths of which are connected in said series with the conduction path of said first transistor; and wherein said first bias means comprises potential divider means coupled at one end thereof to said first terminal and at the other end thereof to said second terminal, said divider means having a plurality of taps at different voltage levels, each tap being coupled to the control electrode of a separate one of said further transistors; and said current mirror amplifier includes a plurality of said output terminals, each coupled to a separate one of said taps.
Claim 4
Dependent Claim 53 words
The combination recited in claim 1 wherein one end of the conduction path of said first transistor is connected to said first terminal and wherein said circuit means comprises a resistor connected between said input terminal of said current mirror amplifier and the other end of the conduction path of said first transistor.
Claim 5
Dependent Claim 32 words
The combination recited in claim 1 wherein said circuit means comprises: first and second resistors connected between said input terminal of said current mirror amplifier and, respectively, said first and second terminals.

References Cited (Backward Citations)

US3546614A Cited
US3622899A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-10-12 1980-04-12 1980-10-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-10-12 1984-04-12 1984-10-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-10-12 1988-04-12 1988-10-12 $7700.00 Window Closed / Lapsed

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