Bias control circuit for an audio amplifier utilizing an unsaturated junction type FET

Claim 1

A bias control circuit for an audio amplifier utilizing an unsaturated junction type FET, the improvement wherein said amplifier includes at least a power amplifier circuit comprising a complementary pair of one N channel and one P channel FETs forming a single ended pushpull circuit, the N channel FET having a drain connected to the positive terminal of a first dc power source of a predetermined voltage and a source connected via a load to a ground potential, and the P channel FET having a drain connected to the negative terminal of the first dc power source and a source connected via the load to the ground potential; and wherein said bias control circuit comprises a series control type constant voltage source constructed of a first complementary pair of one PNP type and one NPN type control transistors, the PNP type control transitor having a collector-emitter path connected between the negative terminal of a second dc power source with its voltage predetermined and varied at subtantially the same rate as that of the first dc power source and the gate of the N channel FET included in said power amplifier circuit and coupled via the gate bias circuit thereof to one terminal of an input audio signal source with the other terminal connected to the ground potential, and the NPN type control transistor having a collector-emitter path connected between the postive terminal of the second dc power source and the gate of the P channel FET included in said power amplifier circuit and coupled via the gate bias circuit thereof to the nongrounded side terminal of the input audio signal source; of a second complementary pair of one PNP type and one NPN type comparison transistors, the PNP type comparison transistor having a base coupled to the base bias circuit thereof forming a first comparator and a collector via a first detection resistor to the negative terminal of the second dc power source coupled with the collector of the PNP type control transistor and connected also to the base thereof, and the NPN comparison transistor having a base coupled to the base bias circuit thereof forming a second comparator and a collector connected via a second detection resistor of substantially the same resistance value as the first detection resistor to the postive terminal of the second dc power source coupled with the collector of the NPN type control transistor and connected also to the base thereof; and of a reference voltage source disposed to induce a reference dc voltage varied at a smaller voltage level than those of the first and second dc power sources in a current conduction path between the positive terminal of the second dc power source and the ground potential and including a series circuit of a voltage regulator element and a third resistor with its nongrounded side terminal connected to the emitter of the NPN type comparison transistor.