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US3984772A Expired / Lapsed US ⏱️ 0.0 years remaining

Signal peak detection arrangement

Assignee: Applied Biosystems Inc
•
Filing: 1974-11-04
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Granted: 1976-10-05
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Expires: 1994-11-04
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Abstract

Abstract A method and apparatus is provided for compensating for repeatable error signal components which occur with information components. The method provides for detecting the peak amplitude of an error signal and providing a representation thereof, storing the representation, providing a composite electrical signal having the information and error components, detecting the peak amplitude of the composite signal and providing a representation thereof, and combining the stored error signal representation with the composite signal representation to provide an output signal from which the error signal component has been substantially removed.

Inventors

  • 👤 Walter Bohler
  • 👤 Duane L. Smith

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 23:22
CPC Classifications
G; G01; G01N; G01N21/00; G01N21/17; G01N21/25; G01N21/31; G01N21/3103; G01R; G01R19/00; G01R19/04

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 173 words
A peak detecting circuit arrangement for compensating for repeatable, relatively short-term error signal components of a composite signal having relatively short-term information and error components comprising: circuit means having a terminal thereof for detecting and providing a signal representative of the peak amplitude of an input signal applied to said terminal; storage circuit means for storing a signal applied thereto; means intercoupling said circuit storage means and said peak detecting circuit means for combining said stored signal in phase opposition with the signal representation of said peak detector means to provide an output signal thereof; and, means for selectively coupling an output signal from said signal combining means to said circuit storage means for selectively storing said output signal in said signal storage means, said peak detection circuit means including polarity sensitive means for detecting the polarity of an applied signal and for providing a signal representative of the peak amplitude and polarity of an applied signal for providing that the stored signal is recombined in phase opposition with a subsequently applied signal.
Claim 2
Dependent Claim 173 words
A peak detecting circuit arrangement for compensating for repeatable, relatively short-term error signal components of a composite signal having relatively short-term information and error components comprising: circuit means having a terminal thereof for detecting and providing a signal representative of the peak amplitude of an input signal applied to said terminal; storage circuit means for storing a signal applied thereto; means intercoupling said circuit storage means and said peak detecting circuit means for combining said stored signal in phase opposition with the signal representation of said peak detector means to provide an output signal thereof; and, means for selectively coupling an output signal from said signal combining means to said circuit storage means for selectively storing said output signal in said signal storage means, said peak detection circuit means including polarity sensitive means for detecting the polarity of an applied signal and for providing a signal representative of the peak amplitude and polarity of an applied signal for providing that the stored signal is recombined in phase opposition with a subsequently applied signal.
Claim 3
Dependent Claim 129 words
The detection arrangement of claim 1 wherein said peak detector comprises a firt peak detector adapted for detecting the peak amplitude of an input signal of a first predetermined polarity; a second peak detector adapted for detecting the peak amplitude of an input signal of a second opposite polarity; switching means responsive to an input signal for alternatively coupling the output signals from said first and second detectors to said signal combination means; comparator circuit means for comparing the amplitude of the output signals from said first and second detectors and for applying an enabling control signal to the switching means associated with the peak detector providing the larger output signal and for disabling the switching means associated with the peak detector providing an output signal of lesser magnitude.
Claim 4
Dependent Claim 67 words
The detection arrangement of claim 2 wherein said storage means comprises an operational amplifier having input and output terminals, said operational amplifier having capacitive feedback means for causing said operational amplifier to operate as an integrating amplifier, means coupling said amplifier output terminal to said signal combining means, and switching means for coupling the output of said signal combining means to the input terminal of said amplifier.

References Cited (Backward Citations)

US3105230A Cited
US3412241A Cited
US3532980A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-10-05 1980-04-05 1980-10-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-10-05 1984-04-05 1984-10-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-10-05 1988-04-05 1988-10-05 $7700.00 Window Closed / Lapsed

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