US3984699A
Expired / Lapsed
US
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Sequence controller
Assignee: Bankers Trust Co
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Filing: 1975-07-14
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Granted: 1976-10-05
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Expires: 1995-07-14
Abstract
Abstract A sequence controller, employing digital techniques, employs clock pulses to energize and deenergize incremental loads sequentially at spaced intervals to correct the deviation of a sensed condition from a setpoint. The clock is inhibited from producing pulses when no deviation requiring correction exists. A feedback provides anticipation for the effect of the energization and deenergization of condition changing loads. Hunting is substantially eliminated.
Inventors
- 👤 Ronald L. Bailey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:38
CPC Classifications
G; G05; G05B; G05B11/00; G05B11/01; G05B11/14; G05B11/18
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
145 words
A sequence controller for digital control of alternative digital output signals employed to control sequential energization and deenergization of a plurality of incremental loads in response to a received variable analog input signal, said sequence controller comprising an input terminal, a plurality of output terminals, a mode reference, comparing means producing a first digital mode response when the input signal received at said input terminal exceeds the mode reference and a second digital mode response when said mode reference exceeds the input signal, a clock producing digital pulses, means for sequentially shifting from a first to a second of said alternative output signals at an additional of said output terminals with each pulse produced by said clock while said first mode response is present, and an inhibitor controlled by said comparing means and coupled to said clock to selectively prevent shifting by the sequencing means.
Claim 2
Dependent Claim
145 words
A sequence controller for digital control of alternative digital output signals employed to control sequential energization and deenergization of a plurality of incremental loads in response to a received variable analog input signal, said sequence controller comprising an input terminal, a plurality of output terminals, a mode reference, comparing means producing a first digital mode response when the input signal received at said input terminal exceeds the mode reference and a second digital mode response when said mode reference exceeds the input signal, a clock producing digital pulses, means for sequentially shifting from a first to a second of said alternative output signals at an additional of said output terminals with each pulse produced by said clock while said first mode response is present, and an inhibitor controlled by said comparing means and coupled to said clock to selectively prevent shifting by the sequencing means.
Claim 3
Dependent Claim
40 words
A sequence controller according to claim 1 wherein said sequencing means shifts from the second to said first of the alternative output signals at an additional of said output terminals with each pulse while said second mode response is present.
Claim 4
Dependent Claim
48 words
A sequence controller according to claim 2 wherein the shifting sequence provided at said output terminals by the sequencing means when shifting from the first to the second output signal is in reverse order to the sequence provided when shifting from the second to the first output signal.
Claim 5
Dependent Claim
72 words
A sequence controller according to claim 1 additionally comprising a high condition reference and a low condition reference coupled to said comparing means, said comparing means producing a first condition response when the input signal exceeds said high condition reference and a second condition response when the low condition reference exceeds said input signal, said inhibitor controlled by absence of both of the condition responses to prevent shifting of said sequencing means.
Claim 6
Dependent Claim
20 words
A sequence controller according to claim 4 wherein said high and low condition references are separated by a fixed deadband.
Claim 7
Dependent Claim
27 words
A sequence controller according to claim 4 wherein said inhibitor comprises an OR-gate, the condition response of said means for comparing supplying the inputs to said OR-gate.
Claim 8
Dependent Claim
23 words
A sequence controller according to claim 4 wherein said inhibitor prevents production of the pulses in absence of both of said condition responses.
Claim 9
Dependent Claim
27 words
A sequence controller according to claim 4 wherein said inhibitor prevents receipt of the pulses by said sequencing means in absence of both of said condition responses.
Claim 10
Dependent Claim
25 words
A sequence controller according to claim 4 wherein said mode reference and one of the high and low condition references are one and the same.
Claim 11
Dependent Claim
24 words
A sequence controller according to claim 4 additionally comprising a plurality of incremental feedback means controlled by said sequencing means for modifying the references.
Claim 12
Dependent Claim
30 words
A sequence controller according to claim 10 wherein said incremental feedback means are added and subtracted in response to the output signals provided to respective ones of said output terminals.
Claim 13
Dependent Claim
26 words
A sequence controller according to claim 11 wherein said feedback means controlled modification of the references is a function of the number of energized feedback means.
Claim 14
Dependent Claim
37 words
A sequence controller according to claim 11 wherein each of said feedback means modifies the references as a function of the condition changing effect of the load connected to that output terminal receiving the respective output signal.
Claim 15
Dependent Claim
22 words
A sequence controller according to claim 11 wherein said mode and condition references are increased and decreased equally by said feedback means.
Claim 16
Independent Claim
125 words
A method for sequentially controlling energization and deenergization of incremental loads comprising the steps of comparing an analog input signal with a mode reference, providing a first mode response when said input signal exceeds the mode reference and a second mode response when said mode reference exceeds the input signal, employing one of said responses to enable sequential energization of the incremental loads and the other of said responses to enable sequential deenergization of the incremental loads, supplying power at spaced intervals to effect enabled energization and deenergization of said incremental loads, and selectively interrupting delivery of the power to effect enabled energization and deenergization of said loads while the input signal exceeds a low condition reference and is exceeded by a high condition reference.
Claim 17
Independent Claim
125 words
A method for sequentially controlling energization and deenergization of incremental loads comprising the steps of comparing an analog input signal with a mode reference, providing a first mode response when said input signal exceeds the mode reference and a second mode response when said mode reference exceeds the input signal, employing one of said responses to enable sequential energization of the incremental loads and the other of said responses to enable sequential deenergization of the incremental loads, supplying power at spaced intervals to effect enabled energization and deenergization of said incremental loads, and selectively interrupting delivery of the power to effect enabled energization and deenergization of said loads while the input signal exceeds a low condition reference and is exceeded by a high condition reference.
Claim 18
Dependent Claim
23 words
A method according to claim 15 additionally comprising incrementally modifying the references as a function of the number of the loads receiving power.
Claim 19
Dependent Claim
25 words
A method according to claim 15 further comprising incrementally modifying the references as a function of the condition changing effect of the loads receiving power.
References Cited (Backward Citations)
US3586869A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-05 | 1980-04-05 | 1980-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-05 | 1984-04-05 | 1984-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-05 | 1988-04-05 | 1988-10-05 | $7700.00 | Window Closed / Lapsed |