US3983334A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Matrix and equalizer circuit with gain control
Assignee: Victor Company of Japan Ltd
•
Filing: 1975-02-21
•
Granted: 1976-09-28
•
Expires: 1995-02-21
Abstract
Abstract A combined matrix and equalizer circuit comprises a matrix circuit for operating with gains on a plurality of input signals. A feedback loop feeds back from a point between output terminals of the matrix circuit and a specific one of the input terminals of the same circuit. The feedback loop causes a signal entering a specific input terminal to have a specific equalizing frequency characteristic.
Inventors
- 👤 Nobuaki Takahashi
- 👤 Yasuo Itoh
- 👤 Masao Kasuga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:07
CPC Classifications
H; H04; H04S; H04S3/00; H04S3/006
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
130 words
A matrix and equalizer circuit comprising: matrix operational circuit means having two input terminals to which are applied, respectively, sum and difference signals derived from first and second channel signals, and two output terminals through which said first and second channel signals are respectively transmitted, means in said matrix for giving gains to said sum and difference signals applied to said input terminals; a pair of resistance elements having equal resistance value connected in series and between said output terminals of said matrix operational circuit means; and a feedback loop connected from a junction of the pair of resistance elements through a capacitor to the input terminal of said sum signal of the matrix operational circuit means, said feedback loop causing said sum signal to have a specific equalizing characteristic.
Claim 2
Dependent Claim
130 words
A matrix and equalizer circuit comprising: matrix operational circuit means having two input terminals to which are applied, respectively, sum and difference signals derived from first and second channel signals, and two output terminals through which said first and second channel signals are respectively transmitted, means in said matrix for giving gains to said sum and difference signals applied to said input terminals; a pair of resistance elements having equal resistance value connected in series and between said output terminals of said matrix operational circuit means; and a feedback loop connected from a junction of the pair of resistance elements through a capacitor to the input terminal of said sum signal of the matrix operational circuit means, said feedback loop causing said sum signal to have a specific equalizing characteristic.
Claim 3
Dependent Claim
26 words
A matrix and equalizer circuit as claimed in claim 1, in which said feedback loop further has a resistance element connected in parallel with said capacitor.
Claim 4
Dependent Claim
26 words
A matrix and equalizer circuit as claimed in claim 1 in which said feedback loop causes said sum signal to have an RIAA roll-off equalizer characteristic.
Claim 5
Dependent Claim
178 words
A matrix and equalizer circuit as claimed in claim 1 in which said means in said matrix for giving gains to said sum and difference signals comprises first operational amplifier means having a positive input terminal connected to one of said two input terminals of said matrix operational circuit means, to which the sum signal is applied, second operational amplifier means having a positive input terminal connected to the other of said two input terminals of said matrix operational circuit means, to which the difference signal is applied, third operational amplifier means having a negative input terminal for receiving the output signal of said first operational amplifier means and a positive input terminal for receiving the output signal of said second operational amplifier means, and fourth operational amplifier means having a negative input terminal for receiving the output signals of the first and second operational amplifier means, said two output terminals of said matrix operational circuit means receiving the output signal of said third operational amplifier means and the output signal of said fourth operational amplifier means respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-28 | 1980-03-29 | 1980-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-28 | 1984-03-29 | 1984-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-28 | 1988-03-29 | 1988-09-28 | $7700.00 | Window Closed / Lapsed |