US3982101A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Laser velocimeter real time digital data analyzer
Assignee: United States Department of the Air Force
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Filing: 1975-05-19
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Granted: 1976-09-21
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Expires: 1995-05-19
Abstract
Abstract A digital analyzer for a laser velocimeter which compresses data into groups for a histogram display. A data processor containing the velocimeter information is fed through a multiplexer to a memory which is controlled by a data interrupt circuit that is fed by a two-phase clock. One phase of the clock pulses an address counter which feeds the multiplexer and a first digital-to-analog converter that controls the x-drive of a cathode ray tube. The data processor also has an output fed to a full adder and then fed back to the memory with the same output being fed to a storage register followed by a second digital-to-analog converter that controls the y-drive of the cathode ray tube.
Inventors
- 👤 Henry T. Kalb
- 👤 Virgil A. Cline, Jr.
- 👤 Bruce W. Bomar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:37
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/18
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
199 words
A digital analyzer for a velocimeter data processor comprising: a. a clock having first and second phase outputs; b. a data interrupt circuit fed by the first and second phase outputs of the clock and activated by a command from the data processor; c. a multiplexer fed by the data processor; d. a random access memory fed by the multiplexer and initiated by the data interrupt circuit and having a readout terminal and a data-in terminal; e. a down counter fed by the command from the data processor; f. a flip-flop activated by the down counter, the output thereof being fed to the multiplexer; g. a full adder fed by the readout terminal of the random access memory and fed back thereto at the data-in terminal; h. an address counter driven by the second phase of the clock and activating the multiplexer; i. a cathode ray tube having an x-deflection terminal and a y-deflection terminal; j. a first digital-to-analog converter fed by the random access memory and connected to the y-deflection terminal of the cathode ray tube; and k. a second digital-to-analog converter fed by the address counter and connected to the x-deflection terminal of the cathode ray tube.
Claim 2
Dependent Claim
199 words
A digital analyzer for a velocimeter data processor comprising: a. a clock having first and second phase outputs; b. a data interrupt circuit fed by the first and second phase outputs of the clock and activated by a command from the data processor; c. a multiplexer fed by the data processor; d. a random access memory fed by the multiplexer and initiated by the data interrupt circuit and having a readout terminal and a data-in terminal; e. a down counter fed by the command from the data processor; f. a flip-flop activated by the down counter, the output thereof being fed to the multiplexer; g. a full adder fed by the readout terminal of the random access memory and fed back thereto at the data-in terminal; h. an address counter driven by the second phase of the clock and activating the multiplexer; i. a cathode ray tube having an x-deflection terminal and a y-deflection terminal; j. a first digital-to-analog converter fed by the random access memory and connected to the y-deflection terminal of the cathode ray tube; and k. a second digital-to-analog converter fed by the address counter and connected to the x-deflection terminal of the cathode ray tube.
Claim 3
Dependent Claim
27 words
A digital analyzer for a velocimeter data processor according to claim 1 which further comprises a data scaling circuit interposed between the data processor and the multiplexer.
Claim 4
Dependent Claim
28 words
A digital analyzer for a velocimeter data processor according to claim 2 which further comprises a storage register interposed between the full adder and the first digital-to-analog converter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-21 | 1980-03-22 | 1980-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-21 | 1984-03-22 | 1984-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-21 | 1988-03-22 | 1988-09-21 | $7700.00 | Window Closed / Lapsed |