Modulator for hybrid modulation by more and less significant digital signals in succession in each clock interval and counterpart demodulator

Claim 1

A modulator for quadrature amplitude modulating a carrier signal having in-phase and quadrature-phase components with an input signal, comprising: a source of clock pulses defining a succession of equal clock intervals, digital signal deriving means responsive to said clock pulses for sampling and quantizing said input signal into a digital signal having a plurality of bits, error signal deriving means responsive to said clock pulses and said input and digital signals for deriving an error signal representative of a quantization error of said digital signal in an associated clock interval, first means for separating said digital signal into more and less significant signals, said more significant signal comprising a predetermined number of the more significant bits of said plurality of bits, said less significant signal comprising the remaining less significant bits of said plurality of bits, second means responsive to said clock pulses for deriving a first signal by arranging said more and less significant signals in time succession in each of said clock intervals, third means responsive to said clock pulses for deriving a second signal by inverting said error signal in a predetermined half of each of said clock intervals and by arranging said error signal and the inverted said error signal in time succession in each said clock interval, and means for simultaneously amplitude modulating each of said in-phase and quadrature-phase components of said carrier signal by one of said first and second signals to generate a quadrature amplitude modulated output signal.