Digital filter for electrical signals

Claim 2

A digital computer filter for electrical signals comprising at least one circuit section without delay elements in the form of a multiport circuit, with a positive port admittance at each port and with an input and output signal quantity at each port at the respective operating times, characterized in that signal quantity modifying port circuits for rounding or chopping of the numbers representing signal quantities are provided in the multiport circuit, and are designed in such a way that the pseudo power p(t m ) received by the multiport circuit at every time t m and which satisfies the relation ##EQU25## where v = number of ports (1, 2, . . . n) a v (t m ) = input signal quantity at the time t m in the v th port b v (t m ) = output signal quantity at the time t m in the v th port G v = port admittance of the v th port is equivalent or only slightly greater than that value of the pseudo power function which results if, by omitting the rounding or chopping circuits, the arithmetic operations are executed with precise accuracy.

Claim 3

A digital computer filter according to claim 1, characterized in that the signal quantity modifying port circuits are designed in such a way that at least at some ports the value of b v (t m ) does not exceed the value which would occur at these ports in the case of an exact execution of the arithmetic operations.

Claim 4

A digital filter for electrical signals comprising at least one circuit section without delay elements in the form of a multiport circuit, each port of said multiport circuit being associated with a positive port admittance and with an input and output signal quantity at the respective operating times, characterized in that the multiport circuit comprises number modifying means operating on selected digit positions of numbers for representing respective signal quantities in such a way that the pseudo power p(t m ) received by the multiport circuit at every time t m and which satisfies the relation ##EQU26## where v = number of ports (1, 2, . . . n) a v (t m ) = input signal quantity at the time t m in the v th port b v (t m ) = output signal quantity at the time t m in the v th port G v = port admittance of the v th port is equivalent or only slightly greater than that value of the pseudo power function which results if, by omitting said number modifying means, the arithmetic operations are executed with precise accuracy.

Claim 5

A digital filter for electrical signals comprising at least one circuit section without delay elements in the form of a multiport circuit, each port of said multiport circuit being associated with a positive port admittance and with an input and output signal quantity at the respective operating times, characterized in that the multiport circuit comprises number modifying means operating on selected digit positions of numbers for representing respective signal quantities in such a way that the pseudo power p(t m ) received by the multiport circuit at every time t m and which satisfies the relation ##EQU26## where v = number of ports (1, 2, . . . n) a v (t m ) = input signal quantity at the time t m in the v th port b v (t m ) = output signal quantity at the time t m in the v th port G v = port admittance of the v th port is equivalent or only slightly greater than that value of the pseudo power function which results if, by omitting said number modifying means, the arithmetic operations are executed with precise accuracy.

Claim 6

A digital filter according to claim 3, characterized in that the number modifying means serves to chop off extreme digit positions of numbers for representing signal quantities at at least certain of the ports such that the output signal quantity b v (t m ) for each of the certain ports does not exceed the value which would occur at such certain ports in the case of an exact execution of the arithmetic operations.

Claim 7

A digital filter comprising an adaptor circuit having a series of ports with respective positive port admittances and having adders and multipliers connected with the respective ports for arithmetically operating on respective port input signal quantities and for supplying respective output signal quantities at respective discrete operating times, and a series of reactance-representing port elements with respective time delays incorporated therein coupled with respective ports of said adaptor circuit and corresponding with respective analog reactances of an analog filter circuit, and means comprising the circuit arrangement of the adders and multipliers and the values of multiplier coefficients for determining values for the port admittances substantially in conformity with the parameter values of the respective analog reactances being represented by the port elements coupled with the respective ports, wherein the improvement comprises number modifying means for selectively digitally modifying the numerical results of the arithmetic operations being supplied to selected ports in said adaptor circuit for achieving a predetermined stability criterion with a substantially reduced word length in comparison to a normal word length required for achieving the predetermined stability criterion while approximating said analog filter circuit substantially as closely as possible.

Claim 8

A digital filter comprising an adaptor circuit having a series of ports with respective positive port admittances and having adders and multipliers connected with the respective ports for arithmetically operating on respective port input signal quantities and for supplying respective output signal quantities at respective discrete operating times, and a series of reactance-representing port elements with respective time delays incorporated therein coupled with respective ports of said adaptor circuit and corresponding with respective analog reactances of an analog filter circuit, and means comprising the circuit arrangement of the adders and multipliers and the values of multiplier coefficients for determining values for the port admittances substantially in conformity with the parameter values of the respective analog reactances being represented by the port elements coupled with the respective ports, wherein the improvement comprises number modifying means for selectively digitally modifying the numerical results of the arithmetic operations being supplied to selected ports in said adaptor circuit for achieving a predetermined stability criterion with a substantially reduced word length in comparison to a normal word length required for achieving the predetermined stability criterion while approximating said analog filter circuit substantially as closely as possible.

Claim 9

A digital filter in accordance with claim 5 with said adaptor circuit including as a constituent thereof a three port adaptor having means including only one multiplier for determining values for the port admittances thereof so as to substantially match the admittances of respective ports connected therewith and for supplying respective output signal quantities to the respective ports thereof, and the number modifying means comprising a device for reducing the word length and changing the value of the output signal quantity supplied to at least one of the ports thereof from a normal value relatively closely approximating that dictated by the parameters of the analog filter circuit to a modified value somewhat less than any approximation of the ideal value.

Claim 10

A digital filter according to claim 5 with the adaptor circuit being free of time delay elements and having an input port for receiving input signal quantities representing an input signal to the analog filter at respective discrete operating times, having an output port, and having interior circuitry corresponding to an analog filter circuit of an order greater than three, and including a plurality of constituent multiport circuits each including said number modifying means for reducing word lengths at the outputs of the respective ports thereof.