Gate modulated bipolar transistor

Claim 2

A gate modulated bipolar transistor including: an emitter region, at least one collector region and at least one gate region integral with a base region; a first region of a first type conductivity as the base region; a second region having a second type conductivity as the emitter region; the first region having two opposed major surfaces; the second region having two opposed major surfaces; the major opposed surfaces being the top and bottom surfaces of the respective regions; the top surface of the second region being coextensive and contiguous with the bottom surface of the first region; a first P-N junction between the top surface of the second region and the bottom surface of the first region; at least one first ohmic electrical contact centrally, disposed upon the top surface of the first region; at least two spaced third regions having second type conductivity as collector regions disposed in a portion of the top surface of the first region wherein the first ohmic contact is centrally disposed therebetween and each region having a selected surface opposed to a selective surface of the other thereby defining the gate region of the device; a second P-N junction between each third and first regions; a second ohmic electrical contact affixed to the bottom surface of the second region; and a third ohmic electrical contact affixed to each of the third regions, and wherein when a variable voltage source, operating between predetermined limits, is connected to the first ohmic contact to drive the gate region and a reverse bias is applied to the collector via the third contacts, an increase in the gate-collector reverse bias decreases the emitter and collector currents and the transistor functions as a negative resistance element, the magnitude of which is modulated by the variable voltage source.

Claim 3

The transistor of claim 1 wherein the third regions are integral with each other to form one region which has an annular configuration which encompasses the gate region.

Claim 4

The transistor of claim 2 and including a plurality of spaced concentric annular third regions disposed in the top surface portion of the first region defining a plurality of spaced annular gate regions; a plurality of first ohmic electrical contacts, each first contact being affixed to a respective one of the gate regions, and a plurality of third ohmic electrical contacts, each third electrical contact being affixed to a respective one of the plurality of third regions.

Claim 5

The transistor of claim 1 including walls defining an annular moat in the outer peripheral portion of the transistor and extending downward from the top surface of the first region to at least intersect, and expose therein, the first P-N junction, and a layer of electrically insulating material disposed on the exposed portions of the first P-N junction in the trough.

Claim 6

The transistor of claim 1 wherein a plurality of third regions are disposed in the portion of the top surface to define a plurality of gate regions, and a plurality of first contacts, each contact is disposed upon a respective gate region defined by a pair of third regions.

Claim 7

The transistor of claim 5 wherein each third region has a rectangular configuration and each gate region has a rectangular configuration.

Claim 8

An electrical circuit including two electrical terminals; a power source; a first electrical circuit means connected between the two electrical terminals and connecting the power source to the electrical load; a gate modulated bipolar transistor including an emitter region and at least one collector region and at least one gate region integral with a base region; a first region of a first type conductivity as the base region; a second region having a second type conductivity as the emitter region; the first region having two opposed major surfaces; the second region having two opposed major surfaces; the major opposed surfaces being the top and bottom surfaces of the respective regions; the top surface of the second region being coextensive and contiguous with the bottom surface of the first region; a first P-N junction between the top surface of the second region and the bottom surface of the first region; at least one first ohmic electrical contact centrally disposed upon the top surface of the first region; at least two spaced third regions having second type conductivity as collector regions disposed in a portion of the top surface of the first region wherein the first ohmic contact is centrally disposed therebetween and each region having a selected side surface opposed to a selective side surface of the other thereby defining the gate region of the device; a second P-N junction between each third and first regions; a second ohmic electrical contact affixed to the bottom surface of the second region; and a third ohmic electrical contact affixed to each of the third regions; a second electrical means connecting the collector region to one of the electrical terminals; a third electrical means connecting the emitter region to the other of the electrical terminals, and a variable voltage source, operating between predetermined limits, connected to drive the at least one gate region, wherein when a reverse bias is applied to the collector an increase in the gate-collector reverse bias decreases the emitter and collector currents and the transistor functions as a negative resistance element, the magnitude of which is modulated by the variable voltage source.

Claim 9

An electrical circuit including two electrical terminals; a power source; a first electrical circuit means connected between the two electrical terminals and connecting the power source to the electrical load; a gate modulated bipolar transistor including an emitter region and at least one collector region and at least one gate region integral with a base region; a first region of a first type conductivity as the base region; a second region having a second type conductivity as the emitter region; the first region having two opposed major surfaces; the second region having two opposed major surfaces; the major opposed surfaces being the top and bottom surfaces of the respective regions; the top surface of the second region being coextensive and contiguous with the bottom surface of the first region; a first P-N junction between the top surface of the second region and the bottom surface of the first region; at least one first ohmic electrical contact centrally disposed upon the top surface of the first region; at least two spaced third regions having second type conductivity as collector regions disposed in a portion of the top surface of the first region wherein the first ohmic contact is centrally disposed therebetween and each region having a selected side surface opposed to a selective side surface of the other thereby defining the gate region of the device; a second P-N junction between each third and first regions; a second ohmic electrical contact affixed to the bottom surface of the second region; and a third ohmic electrical contact affixed to each of the third regions; a second electrical means connecting the collector region to one of the electrical terminals; a third electrical means connecting the emitter region to the other of the electrical terminals, and a variable voltage source, operating between predetermined limits, connected to drive the at least one gate region, wherein when a reverse bias is applied to the collector an increase in the gate-collector reverse bias decreases the emitter and collector currents and the transistor functions as a negative resistance element, the magnitude of which is modulated by the variable voltage source.

Claim 10

The transistor of claim 7 wherein the third regions are integral with each other to form one region which has an annular configuration which encompasses the gate region.

Claim 11

The transistor of claim 8 and including a plurality of spaced concentric annular third regions disposed in the top surface portion of the first region defining a plurality of spaced annular gate regions; a plurality of first ohmic electrical contacts, each first contact being affixed to a respective one of the gate regions, and a plurality of third ohmic electrical contacts, each third electrical contact being affixed to a respective one of the pluraity of third regions.

Claim 12

The transistor of claim 7 wherein a plurality of third regions are disposed in the portion of the top surface to define a plurality of gate regions, and a plurality of first contacts, each contact is disposed upon a respective gate region defined by a pair of third regions.

Claim 13

The transistor of claim 10 wherein each third region has a rectangular configuration and each gate region has a rectangular configuration.

Claim 14

The transistor of claim 7 including walls defining an annular moat in the outer peripheral portion of the transistor and extending downward from the top surface of the first region to at least intersect, and expose therein, the first P-N junction, and a layer of electrically insulating material disposed on the exposed portions of the first P-N junction in the trough.