Controlled fading switching circuit

Claim 2

A semiconductor switch comprising a semiconductor channel region of first impurity type having a planar surface and having source and drain regions therein, a gate region of second impurity type extending partially into said channel region from said planar surface between said source and drain regions to form a junction with a portion of said channel region, an auxiliary region of the first impurity type extending partially into said gate region and forming a junction therewith, a gate bias source, a switch connecting said gate bias source to said auxiliary region to forwardly bias the junction between said auxiliary region and said gate region and reversely bias the junction between said gate region and said channel region, whereby when said switch is closed a depletion region is formed at least partially across said channel region which increases the source to drain resistance, an emitter region of the second impurity type extending partially into said channel region from said planar surface, a current source connected to said emitter region which is poled to cause minority carriers to be injected into said depletion region for neutralizing stored charges therein to decrease the source to drain resistance for effecting a fade time, and a channel region biasing circuit connected between said source and drain regions having an input terminal at said source and an output terminal at said drain.

Claim 3

A semiconductor switch according to claim 1, wherein said first impurity type is N-type and said second inpurity type is P-type.

Claim 4

A semiconductor switch according to claim 2, in which said source, drain, auxiliary and emitter regions are each provided with an electrode, said source electrode being connected to an input terminal and to ground through a first resistor, said drain electrode being connected to an output terminal and through a second resistor and battery to ground, and said auxiliary electrode being connected through a switch and battery to ground, the negative side of said first battery and the positive side of said second battery being on the ground side.

Claim 5

A switching circuit adapted for providing an adjustable fading time during a switching operation comprising: a. a charge storage junction field effect transistor having i. a semiconductor channel region of first conductivity type, ii. a first semiconductor region of second conductivity type diffused in a portion of said channel region to form a charge storage first PN junction; iii. a second semiconductor region of first conductivity type diffused in said first region to form a second PN junction, iv. a gate electrode connected to said second region, v. a source electrode and a drain electrode connected to said channel region with said gate electrode therebetween, and vi. a carrier injection region of second conductivity type adjacent said first semiconductor region; b. an input circuit connected to said source electrode; c. a channel region biasing circuit connected between said source and drain electrodes and having an input terminal at said source electrode and an output terminal at said drain electrode; d. a gate bias supply switchably connected between said gate electrode and channel biasing circuit for applying forward bias to said second PN junction and reverse bias to said charge storage first PN junction when said gate bias supply is connected; and e. an injection current source connected to said carrier injection region for controllably neutralizing stored charge in said first semiconductor region over a predetermined fading time when said gate bias supply is disconnected.

Claim 6

A switching circuit adapted for providing an adjustable fading time during a switching operation comprising: a. a charge storage junction field effect transistor having i. a semiconductor channel region of first conductivity type, ii. a first semiconductor region of second conductivity type diffused in a portion of said channel region to form a charge storage first PN junction; iii. a second semiconductor region of first conductivity type diffused in said first region to form a second PN junction, iv. a gate electrode connected to said second region, v. a source electrode and a drain electrode connected to said channel region with said gate electrode therebetween, and vi. a carrier injection region of second conductivity type adjacent said first semiconductor region; b. an input circuit connected to said source electrode; c. a channel region biasing circuit connected between said source and drain electrodes and having an input terminal at said source electrode and an output terminal at said drain electrode; d. a gate bias supply switchably connected between said gate electrode and channel biasing circuit for applying forward bias to said second PN junction and reverse bias to said charge storage first PN junction when said gate bias supply is connected; and e. an injection current source connected to said carrier injection region for controllably neutralizing stored charge in said first semiconductor region over a predetermined fading time when said gate bias supply is disconnected.

Claim 7

The switching circuit of claim 4 in which said channel region biasing circuit comprises a resistor connected to said source electrode and a power source in series with a resistor connected to said drain.

Claim 8

The switching circuit of claim 4 in which said gate bias supply comprises a series connection of a bias source and switch.

Claim 9

A switching circuit adapted for providing an adjustable fading time during a switching operation comprising: a. a charge storage junction field effect transistor having source, drain, gate, and discharge electrodes connected thereto; b. a junction field effect transistor having source, drain, and gate electrodes connected thereto, said source electrode being connected to said discharge electrode and said drain electrode being connected to a reference terminal; c. a controllable bias source connected between a reference terminal and said junction field effect transistor gate for establishing the fading time; d. input and output bias circuits connected between the reference terminal and the source and drain electrodes respectively of said charge storage junction field effect transistor; and e. a switchable bias circuit connected between said charge storage junction field effect transistor and the reference terminal; whereby said junction field effect transistor controllably neutralizes stored charge in said charge storage junction field effect transistor to determine fading time when said switchable bias circuit is switched.

Claim 10

A switching circuit adapted for providing an adjustable fading time during a switching operation comprising: a. a charge storage junction field effect transistor having source, drain, gate, and discharge electrodes connected thereto; b. a junction field effect transistor having source, drain, and gate electrodes connected thereto, said source electrode being connected to said discharge electrode and said drain electrode being connected to a reference terminal; c. a controllable bias source connected between a reference terminal and said junction field effect transistor gate for establishing the fading time; d. input and output bias circuits connected between the reference terminal and the source and drain electrodes respectively of said charge storage junction field effect transistor; and e. a switchable bias circuit connected between said charge storage junction field effect transistor and the reference terminal; whereby said junction field effect transistor controllably neutralizes stored charge in said charge storage junction field effect transistor to determine fading time when said switchable bias circuit is switched.

Claim 11

A switching circuit adapted for providing an adjustable fading time during a switching operation comprising: a. a field effect transistor having source, gate, and drain electrodes connected thereto; b. a charge storage diode having a first electrode connected to said field effect transistor gate, said diode also having a second electrode; c. a carrier injection means connected between a reference and said charge storage diode to controllably inject carriers into said charge storage diode to determine fade time of the charge stored in said diode; d. a switchable bias source between a reference and said charge storage diode second electrode; and e. input and output bias circuits connected between a reference terminal and the source and drain electrodes, respecitvely; whereby the charge stored in said charge storage diode is controllably discharged to change the bias on the gate of said field effect transistor according to a fade time determined by said carrier injection means.

Claim 12

A switching circuit adapted for providing an adjustable fading time during a switching operation comprising: a. a field effect transistor having source, gate, and drain electrodes connected thereto; b. a charge storage diode having a first electrode connected to said field effect transistor gate, said diode also having a second electrode; c. a carrier injection means connected between a reference and said charge storage diode to controllably inject carriers into said charge storage diode to determine fade time of the charge stored in said diode; d. a switchable bias source between a reference and said charge storage diode second electrode; and e. input and output bias circuits connected between a reference terminal and the source and drain electrodes, respecitvely; whereby the charge stored in said charge storage diode is controllably discharged to change the bias on the gate of said field effect transistor according to a fade time determined by said carrier injection means.