Patent US3735425A successfully refreshed from Google Patents.
US3979683A
Expired / Lapsed
US
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Noise eliminator circuit
Assignee: Hitachi Ltd
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Filing: 1975-01-06
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Granted: 1976-09-07
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Expires: 1995-01-06
Abstract
Abstract A noise eliminator circuit comprises a detector which detects whether or not the incoming signal exceeds a prescribed level, and an eliminator which eliminates noise signals above the predetermined level. Delay circuitry is coupled between the detector and the eliminator in order to prevent time delays from the point of detection to the point of noise elimination from interferring with the cancellation of the noise components.
Inventors
- 👤 Tsuneo Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:49
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
96 words
In a noise eliminator circuit comprising: an input terminal to which an input signal from which a noise signal is to be removed is applied; an output terminal; first means, coupled to said input terminal, for detecting the existence of noise in said input signal; and second means, coupled to said first means, for removing said noise from said input signal and coupling the resulting signal to said output terminal; the improvement comprising third means, coupled between said input terminal and said second means, for delaying the application of said input signal to said second means.
Claim 2
Dependent Claim
96 words
In a noise eliminator circuit comprising: an input terminal to which an input signal from which a noise signal is to be removed is applied; an output terminal; first means, coupled to said input terminal, for detecting the existence of noise in said input signal; and second means, coupled to said first means, for removing said noise from said input signal and coupling the resulting signal to said output terminal; the improvement comprising third means, coupled between said input terminal and said second means, for delaying the application of said input signal to said second means.
Claim 3
Dependent Claim
51 words
The improvement according to claim 1, wherein said first means comprises a comparator circuit having first and second inputs and an output, its first input being coupled to said input terminal, its second input being coupled to receive a prescribed voltage level and its output being coupled to said second means.
Claim 4
Dependent Claim
49 words
The improvement according to claim 1, wherein said second means comprises a gate circuit having first and second inputs and an output, its first input being coupled to said third means, its second input being coupled to said first means, and its output being coupled to said output terminal.
Claim 5
Dependent Claim
33 words
The improvement according to claim 2, further including a voltage level generating circuit coupled between said output terminal and the second input of said comparator circuit for supplying said prescribed voltage level thereto.
Claim 6
Dependent Claim
35 words
The improvement according to claim 1, wherein said third means comprises a delay circuit, the delay period provided by which is no greater than the period of the detection carried out by said first means.
Claim 7
Dependent Claim
52 words
The improvement according to claim 2, wherein said second means comprises a gate circuit having first and second inputs and an output, its first input being coupled to said third means, its second input being coupled to the output of said comparator circuit, and its output being coupled to said output terminal.
Claim 8
Dependent Claim
33 words
The improvement according to claim 6, further including a voltage level generating circuit coupled between said output terminal and the second input of said comparator circuit for supplying said prescribed voltage level thereto.
Claim 9
Dependent Claim
34 words
The improvement according to claim 7, wherein third means comprises a delay circuit, the delay period provided by which is no greater than the period of the detection carried out by said comparator circuit.
Claim 10
Dependent Claim
49 words
The improvement according to claim 1, wherein said second means comprises an inverter circuit having an input, a control terminal and an output, its input being coupled to said input terminal, its control terminal being coupled to said first means, and its output being coupled to said output terminal.
Claim 11
Dependent Claim
55 words
The improvement according to claim 9, wherein said first means comprises a comparator circuit having first and second inputs and an output, its first input being coupled to said input terminal, its second input being coupled to receive a prescribed voltage level and its output being coupled to the control terminal of said inverter circuit.
Claim 12
Dependent Claim
33 words
The improvement according to claim 10, further including a voltage level generating circuit coupled between said output terminal and the second input of said comparator circuit for supplying said prescribed voltage level thereto.
Claim 13
Dependent Claim
34 words
The improvement according to claim 11, wherein third means comprises a delay circuit, the delay period provided by which is no greater than the period of the detection carried out by said comparator circuit.
Claim 14
Dependent Claim
113 words
In a noise eliminator circuit comprising: an input terminal to which an input signal from which a noise signal is to be removed is applied; an output terminal; first means, coupled to said input terminal, for detecting the existence of noise in said input signal; and second means, coupled to said first means, for removing said noise from said input signal and coupling the resulting sigal to said output terminal; the improvement comprising third means, coupled between said input terminal and said second means, having a delay time which is substantially equal to the operation delay time of said first means, for delaying the application of said input signal to said second means.
Claim 15
Dependent Claim
113 words
In a noise eliminator circuit comprising: an input terminal to which an input signal from which a noise signal is to be removed is applied; an output terminal; first means, coupled to said input terminal, for detecting the existence of noise in said input signal; and second means, coupled to said first means, for removing said noise from said input signal and coupling the resulting sigal to said output terminal; the improvement comprising third means, coupled between said input terminal and said second means, having a delay time which is substantially equal to the operation delay time of said first means, for delaying the application of said input signal to said second means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-07 | 1980-03-08 | 1980-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-07 | 1984-03-08 | 1984-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-07 | 1988-03-08 | 1988-09-07 | $7700.00 | Window Closed / Lapsed |