US3978477A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic test sequence circuit for a security system
Assignee: Westinghouse Electric Corp
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Filing: 1975-05-29
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Granted: 1976-08-31
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Expires: 1995-05-29
Abstract
Abstract In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions and a corresponding plurality of resettable latching circuits for developing digital output signals indicative of alarm conditions for processing by logic circuits to develop alarm output signals, an automatic test circuit responds to a single activating signal by sequentially supplying simulated alarm condition signals to the respective latching circuits to determine the operational integrity of the latching and logic circuits. At the conclusion of the test sequence the automatic test circuit transmits reset signals to the resettable latching circuits.
Inventors
- 👤 Lawrence S. Schmitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:48
CPC Classifications
G; G08; G08B; G08B29/00; G08B29/02; G08B29/06; G08B29/08; G08B29/12; G08B29/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing a digital output signal indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having an input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means automatically supplying reset signals to said plurality of resettable latching circuit means following the sequential application of said simulated alarm condition signals.
Claim 2
Dependent Claim
148 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing a digital output signal indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having an input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means automatically supplying reset signals to said plurality of resettable latching circuit means following the sequential application of said simulated alarm condition signals.
Claim 3
Dependent Claim
181 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing digital output signals indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having a first input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means including a second input, said output circuit means developing an alarm digital output signal indicative of the presence of an actual alarm condition, said alarm digital output signal being supplied to said second input of said test circuit means to inhibit the application of simulated alarm condition signals when an actual alarm condition is present.
Claim 4
Dependent Claim
181 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing digital output signals indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having a first input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means including a second input, said output circuit means developing an alarm digital output signal indicative of the presence of an actual alarm condition, said alarm digital output signal being supplied to said second input of said test circuit means to inhibit the application of simulated alarm condition signals when an actual alarm condition is present.
Claim 5
Dependent Claim
152 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing digital output signals indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having a first input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means including a second input, and clock means connected to said second input to control the sequential rate at which said simulated alarm conditions signals are supplied.
Claim 6
Dependent Claim
152 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing digital output signals indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having a first input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means including a second input, and clock means connected to said second input to control the sequential rate at which said simulated alarm conditions signals are supplied.
Claim 7
Dependent Claim
236 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing digital output signals indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having a first input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means including a second input, clock means connected to said second input to control the sequential rate at which said simulated alarm conditions signals are supplied, said test circuit means including a third input, said output circuit means developing an alarm digital output signal indicative of the presence of an actual alarm condition, said alarm digital output signal being supplied to said third input of said test circuit means to inhibit the application of simulated alarm condition digital signals when an actual alarm condition is present, said test circuit means automatically supplying reset signals to said plurality of resettable latching circuits means following the application of said simulated alarm condition signals.
Claim 8
Dependent Claim
236 words
In a solid state security system having a plurality of alarm sensors for generating output signals in response to alarm conditions, a plurality of resettable latching circuit means responding to said output signals of said sensors by producing digital output signals indicative of said alarm conditions, and output circuit means adapted to respond to said digital output signals by providing a manifestation of said alarm conditions, the combination of, a test circuit means having a first input adapted to respond to a single input signal by sequentially supplying simulated alarm condition signals to said plurality of resettable latching circuit means to activate said output circuit means to monitor the operational integrity of the respective resettable latching circuit means and output circuit means, said test circuit means including a second input, clock means connected to said second input to control the sequential rate at which said simulated alarm conditions signals are supplied, said test circuit means including a third input, said output circuit means developing an alarm digital output signal indicative of the presence of an actual alarm condition, said alarm digital output signal being supplied to said third input of said test circuit means to inhibit the application of simulated alarm condition digital signals when an actual alarm condition is present, said test circuit means automatically supplying reset signals to said plurality of resettable latching circuits means following the application of said simulated alarm condition signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-31 | 1980-03-01 | 1980-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-31 | 1984-03-01 | 1984-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-31 | 1988-03-01 | 1988-08-31 | $7700.00 | Window Closed / Lapsed |