US3978451A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controlling communications between computer devices over common bus
Assignee: RCA Corp
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Filing: 1975-04-21
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Granted: 1976-08-31
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Expires: 1995-04-21
Abstract
Abstract A system for controlling communications between a plurality of computer devices via a common bus. The bus includes a multi-conductor data bus and lines for busy, strobe and acknowledge signals. The system involves one universal interface unit associated with each respective computer device. Each device can initiate access to the common bus, through its respective interface unit, on a first-come, first-served basis.
Inventors
- 👤 Roy Atsushi Ito
- 👤 Gary Arthur Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:30
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/374; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213; H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/407
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
192 words
A system for controlling communications between a plurality of devices via a common bus which includes a multi-conductor data bus, and a "busy" bus, comprising a plurality of interface units each associated with a respective device, each interface unit including a data transceiver for transferring data between the respective device and the data bus, an address recognizer providing an "address match" output signal when receptive to an address from the respective device and said data bus which matches the address of the respective device, means including a "busy" flip-flop responsive to a bus access "request" signal from the respective device, and to the absence of a busy signal on the busy bus, to put a busy signal on the busy bus, and to enable the data transceiver to connect the address of the respective device to the data bus, and means including a "grant" flip-flop responsive to an address match signal from said address recognizer to supply a "grant" signal to the respective device to signal the seizing of the bus by the respective device, and to continue the supplying of a busy signal to the busy bus from said "busy" flip-flop.
Claim 2
Independent Claim
192 words
A system for controlling communications between a plurality of devices via a common bus which includes a multi-conductor data bus, and a "busy" bus, comprising a plurality of interface units each associated with a respective device, each interface unit including a data transceiver for transferring data between the respective device and the data bus, an address recognizer providing an "address match" output signal when receptive to an address from the respective device and said data bus which matches the address of the respective device, means including a "busy" flip-flop responsive to a bus access "request" signal from the respective device, and to the absence of a busy signal on the busy bus, to put a busy signal on the busy bus, and to enable the data transceiver to connect the address of the respective device to the data bus, and means including a "grant" flip-flop responsive to an address match signal from said address recognizer to supply a "grant" signal to the respective device to signal the seizing of the bus by the respective device, and to continue the supplying of a busy signal to the busy bus from said "busy" flip-flop.
Claim 3
Dependent Claim
30 words
A system according to claim 1 wherein said means including a "grant" flip-flop also includes means to disable the data transceiver connection of the device address to the data bus.
Claim 4
Dependent Claim
60 words
A system according to claim 2, and in addition, clock means by which events are made to occur at predetermined times, so that the bus access "request" signal can be continued until the absence of a busy signal on the busy bus, and the presence of an "address match" signal, permits the seizing of the bus by the requesting device.
Claim 5
Dependent Claim
33 words
A system according to claim 3 wherein said address recognizer consists of gates each having one input wired according to the respective device address, and having another input coupled to the data bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-31 | 1980-03-01 | 1980-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-31 | 1984-03-01 | 1984-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-31 | 1988-03-01 | 1988-08-31 | $7700.00 | Window Closed / Lapsed |