US3975898A
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Electronic timepiece
Assignee: Suwa Seikosha KK
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Filing: 1975-07-11
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Granted: 1976-08-24
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Expires: 1995-07-11
Abstract
Abstract An electronic timepiece including a variable divider for producing timekeeping signals for the smallest digit of time displayed having a frequency which is not evenly divisible into the frequency produced by the time standard. An oscillator includes a time standard for producing a high frequency time standard signal having a frequency of K N Hz where K and N are positive integers other than O, and a divider adapted to evenly divide the high frequency time standard signal by K M , where M is an integer other than O, and in response thereto produce a K N -M frequency signal having a frequency not evenly divisible by I P , where I is a positive integer other than K and P is an integer. A counter is provided for producing output signals representative of a counting cycle in response to an input pulse signal applied thereto, and a display device is coupled to the counter for displaying each count of the cycle thereof. A detecting circuit is coupled to the counter to detect at least one predetermined count of each counting cycle thereof, and in response to each predetermined count produces a detection pulse. The variable divider is coupled to the detection circuit and has a first and second division ratio. The variable divider is adapted to receive the K N -M frequency signal and in response thereto divides same by a first division ratio, and in response to each said detection pulse applied thereto divides the K N -M frequency pulse by said second division ratio to thereby produce an input pulse signal to the counter having a frequency evenly divisible by I P .
Inventors
- 👤 Izuhiko Nishimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:08
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04G3/022; G04F; G04F10/00; G04F10/04; H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
240 words
In an electronic timepiece including an oscillator means for producing a high frequency time standard signal having a frequency of K N Hz , where K and N are positive integers other than zero, and divider means adapted to evenly divide said high frequency time standard signal by K M , where M is an integer other than zero, and produce a K N -M frequency signal having a frequency not evenly divisible by I P , where I is a positive integer other than K and P is an integer, counter means adapted to produce output signals representative of a counting cycle in response to an input pulse signal applied thereto, and display means coupled to said counter means for displaying each count of the cycle thereof, the improvement comprising detecting means for detecting at least one predetermined count of each counting cycle thereof, and in response to each predetermined count detected, producing a detection pulse, and variable divider means coupled to said detection means and having a first and second division ratio, said varible divider means being adapted to receive said K N1/3M frequency signal and in response thereto divide same by a first division ratio and in response to each said detection pulse applied thereto divide said K N -M frequency signal by said second division ratio, to thereby apply an input pulse signal to said counter means having a frequency evenly divisible by I P .
Claim 2
Dependent Claim
240 words
In an electronic timepiece including an oscillator means for producing a high frequency time standard signal having a frequency of K N Hz , where K and N are positive integers other than zero, and divider means adapted to evenly divide said high frequency time standard signal by K M , where M is an integer other than zero, and produce a K N -M frequency signal having a frequency not evenly divisible by I P , where I is a positive integer other than K and P is an integer, counter means adapted to produce output signals representative of a counting cycle in response to an input pulse signal applied thereto, and display means coupled to said counter means for displaying each count of the cycle thereof, the improvement comprising detecting means for detecting at least one predetermined count of each counting cycle thereof, and in response to each predetermined count detected, producing a detection pulse, and variable divider means coupled to said detection means and having a first and second division ratio, said varible divider means being adapted to receive said K N1/3M frequency signal and in response thereto divide same by a first division ratio and in response to each said detection pulse applied thereto divide said K N -M frequency signal by said second division ratio, to thereby apply an input pulse signal to said counter means having a frequency evenly divisible by I P .
Claim 3
Dependent Claim
12 words
An electronic timepiece as claimed in claim 1, wherein I = 10.
Claim 4
Dependent Claim
22 words
An electronic timepiece as claimed in claim 2, wherein said counter means is a decimal counter having a counting cycle of 10.
Claim 5
Dependent Claim
12 words
An electronic timepiece as claimed in claim 3, wherein K = 2.
Claim 6
Dependent Claim
16 words
An electronic timepiece as claimed in claim 4, wherein N = 15, and M = 8.
Claim 7
Dependent Claim
34 words
An electronic timepiece as claimed in claim 5, wherein said first division ratio is 1/13, and said second division ratio is 1/12 and said predetermined counts of said counting cycle are 3 and 8.
Claim 8
Dependent Claim
66 words
An electronic timepiece as claimed in claim 3, and including a plurality of series-connected chronographic counters coupled to said counter means for producing chronographic signals in response to an output signal produced by said counter means and further display means associated with each said counter means for displaying the count thereof, said first display means and further display means effecting a chronographic display of elapsed time.
Claim 9
Dependent Claim
77 words
An electronic timepiece as claimed in claim 7, and including timekeeping divider means adapted to receive said K N -M frequency signal and divide same by K N -M to produce a 1 Hz low frequency signal, series-connected timekeeping counter means adapted to receive said 1 Hz signal and in response thereto produce timekeeping signals representative of present time, and display means associated with each said series-connected timekeeping counter means for displaying the timekeeping signals produced thereby.
Claim 10
Dependent Claim
12 words
An electronic timepiece as claimed in claim 8, wherein P = 1.
Claim 11
Dependent Claim
143 words
An electronic timepiece as claimed in claim 1, wherein said variable divider means includes series-connected flip-flop means adapted to receive said K N -M frequency signal and in response to each pulse thereof effect an indexing of the binary count thereof by 1, said detecting means including first circuit means coupled to said variable divider flip-flop means for detecting a first predetermined binary count thereof and in response to detecting said predetermined binary count producing a reset pulse, and reset pulse means adapted to receive said reset pulse and in response thereto apply a resetting pulse to said variable divider flip-flop means to reset the count thereof to zero, said variable divider flip-flop means producing an output pulse in response to resetting of the count thereof having a frequency equal to the K N -M frequency signal divider by said first division ratio.
Claim 12
Dependent Claim
76 words
An electronic timepiece as claimed in claim 10, wherein said counter means includes series-connected flip-flop means for receiving said input pulse signals and in response to each pulse thereof effect an indexing of the binary count thereof to count through said counting cycle, said counting cycle being equal to I, and in response to said counter flip-flop means counting through said counting cycle produce an output signal having a frequency equal to I P -I Hz.
Claim 13
Dependent Claim
133 words
An electronic timepiece as claimed in claim 11, wherein said detection means for detecting a predetermined count of each counting cycle includes a second circuit means coupled to said variable divider flip-flop means for detecting a further binary count thereof, and in response to the coincident detection of each predetermined count of said counting cycle, and said further binary count of said variable divider flip-flop means, apply a reset pulse to said reset means to cause same to immediately apply said resetting signal to said variable divider flip-flop means and reset the count of said variable divider means to zero, said variable divider flip-flop means producing an output pulse in response to resetting of the count thereof having a frequency equal to the K N -M frequency divided by said second division ratio.
Claim 14
Dependent Claim
42 words
An electronic timepiece as claimed in claim 12, wherein said variable divider flip-flop means is comprised of four series-connected flip-flops, the predetermined binary counts thereof at which same are reset defining respective division ratios of 1/B-1, where B is a positive integer.
Claim 15
Dependent Claim
33 words
An electronic timepiece as claimed in claim 13, wherein K = 2, N-M = 128, and the respective first and second predetermined counts of said variable divider flip-flop means are 14 and 13.
Claim 16
Dependent Claim
82 words
An electronic timepiece as claimed in claim 14, wherein said counter flip-flop means are comprised of four series-connected data-type flip-flops and feedback means coupled to write-in terminal thereof to produce a counting cycle of 10, the counts of 3 and 8 being the predetermined counts detected by said detecting means, said second detection circuit means in response to the detection of said respective 3 and 8 counts and said predetermined binary count of 13, effecting resetting of said variable divider flip-flop means.
Claim 17
Dependent Claim
104 words
An electronic timepiece as claimed in claim 12, wherein said reset means includes set-reset flip-flop means, said set-reset flip-flop means being adapted to receive said K N -M frequency signal, and in response to each said reset pulse applied thereto being set to apply said resetting pulse to said variable divider flip-flop means to effect resetting of the count thereof to zero, and in response to the next pulse of the K N -M frequency signal applied thereto, being reset to thereby terminate the application of said resetting pulse to thereby terminate the application of said resetting pulse to said variable divider flip-flop means.
Claim 18
Dependent Claim
245 words
In an electronic timepiece including oscillator means for producing a high frequency time standard signal having a frequency of 2 N Hz, where N is an integer other than zero, divider means adapted to receive said high frequency time standard signal and in response thereto produce a 2 N -M frequency signal having a frequency not evenly divisible by 10 P , where M and P are integers other than zero, first timekeeping divider means including series-connected binary divider stages for receiving said 2 N -M frequency signal and in response thereto produce a low frequency timekeeping signal, and a plurality of series-connected counter means for producing output signals representative of present time, and display means, coupled to said counter means for displaying present time in response to signals produced thereby, the improvement comprising detecting means coupled to said timekeeping divider means for detecting at least one predetermined state of said divider stages comprising said divider timekeeping means, and in response thereto producing a detection pulse, and variable divider means coupled to said detection means and having a first and second division ratio, said variable divider means being adapted to receive said 2 N -M frequency signal and in response thereto divide same by a first division ratio and in response to each said detection pulse applied thereto divide said 10 N -M frequency pulse by said second division ratio, to thereby produce an output signal having a frequency evenly divisible by 10 P Hz.
Claim 19
Dependent Claim
245 words
In an electronic timepiece including oscillator means for producing a high frequency time standard signal having a frequency of 2 N Hz, where N is an integer other than zero, divider means adapted to receive said high frequency time standard signal and in response thereto produce a 2 N -M frequency signal having a frequency not evenly divisible by 10 P , where M and P are integers other than zero, first timekeeping divider means including series-connected binary divider stages for receiving said 2 N -M frequency signal and in response thereto produce a low frequency timekeeping signal, and a plurality of series-connected counter means for producing output signals representative of present time, and display means, coupled to said counter means for displaying present time in response to signals produced thereby, the improvement comprising detecting means coupled to said timekeeping divider means for detecting at least one predetermined state of said divider stages comprising said divider timekeeping means, and in response thereto producing a detection pulse, and variable divider means coupled to said detection means and having a first and second division ratio, said variable divider means being adapted to receive said 2 N -M frequency signal and in response thereto divide same by a first division ratio and in response to each said detection pulse applied thereto divide said 10 N -M frequency pulse by said second division ratio, to thereby produce an output signal having a frequency evenly divisible by 10 P Hz.
Claim 20
Dependent Claim
19 words
An electronic timepiece as claimed in claim 17, wherein N = 15, M = 8, and P = 1.
Claim 21
Dependent Claim
33 words
An electronic timepiece as claimed in claim 18, and including chronographic counter means adapted to receive said variable divider means output signal and in response thereto produce chronographic signals representative of elapsed time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-24 | 1980-02-23 | 1980-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-24 | 1984-02-23 | 1984-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-24 | 1988-02-23 | 1988-08-24 | $7700.00 | Window Closed / Lapsed |