US3975624A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two's complement subtracting system
Assignee: United States Department of the Air Force
•
Filing: 1975-05-19
•
Granted: 1976-08-17
•
Expires: 1995-05-19
Abstract
Abstract A two's complement subtractor using a one bit full adder for the most significant bit. A series of arithmetic logic units are fed by the respective binary bits to be subtracted with the logic units effecting internal two's complementing of the subtrahend thereby permitting adding to the minuend. The most significant input bits are in addition fed to a one bit full adder together with the carry in bit from the last arithmetic logic unit of the series. The one bit full adder outputs the most significant bit or the sign resulting from the subtraction and this adder can have either internal inversion of the subtrahend or an inverter can precede the subtrahend input.
Inventors
- 👤 Darrell R. Kay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:50
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/499; G06F7/49994
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
131 words
A two's complement system for subtracting a subtrahend from a minuend comprising: a. a series of interconnected four bit full adders each having a minuend input and a subtrahend input with the first of the series corresponding to the least significant bits of the minuend and the subtrahend and the last of the series corresponding to the most significant bits of the minuend and the subtrahend; and b. a one bit full adder forming an additional stage in the series of four bit full adders, fed by the sign bits of the minuend and the subtrahend and the carry output of the four bit full adder corresponding to the most significant bit for forming a sign bit with the one bit full adder having an internal inverter for the sum output.
Claim 2
Dependent Claim
131 words
A two's complement system for subtracting a subtrahend from a minuend comprising: a. a series of interconnected four bit full adders each having a minuend input and a subtrahend input with the first of the series corresponding to the least significant bits of the minuend and the subtrahend and the last of the series corresponding to the most significant bits of the minuend and the subtrahend; and b. a one bit full adder forming an additional stage in the series of four bit full adders, fed by the sign bits of the minuend and the subtrahend and the carry output of the four bit full adder corresponding to the most significant bit for forming a sign bit with the one bit full adder having an internal inverter for the sum output.
Claim 3
Dependent Claim
124 words
A two's complement system for subtracting a subtrahend from a minuend comprising: a. a series of interconnected four bit full adders each having a minuend input and a subtrahend input with the first of the series corresponding to the least significant bit and the last of the series corresponding to the most significant bits of the minuend and the subtrahend b. one bit full adder forming an additional stage in the series of four bit full adders and fed by the sign bits of the minuend and the subtrahend and the carry output of the four bit full adder corresponding to the most significant bit for forming a sign bit; and c. an inverter preceding the subtrahend input to the one bit full adder.
Claim 4
Dependent Claim
124 words
A two's complement system for subtracting a subtrahend from a minuend comprising: a. a series of interconnected four bit full adders each having a minuend input and a subtrahend input with the first of the series corresponding to the least significant bit and the last of the series corresponding to the most significant bits of the minuend and the subtrahend b. one bit full adder forming an additional stage in the series of four bit full adders and fed by the sign bits of the minuend and the subtrahend and the carry output of the four bit full adder corresponding to the most significant bit for forming a sign bit; and c. an inverter preceding the subtrahend input to the one bit full adder.
References Cited (Backward Citations)
US3196262A
Cited
US3816734A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-17 | 1980-02-16 | 1980-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-17 | 1984-02-16 | 1984-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-17 | 1988-02-16 | 1988-08-17 | $7700.00 | Window Closed / Lapsed |